Semiconductor Components Industries, LLC

Tetsuro Hirano

Kiyofumi Nakaya

Shuji Fujiwara

Kyouichi Kashima

Masahiro Ono

Yoshitaka Fukushima

A circuit device connected between a neighboring pair of terminals in a semiconductor integrated circuit is protected from electrostatic damage due to a surge voltage when the surge voltage is applied between the neighboring pair of terminals. The semiconductor integrated circuit is formed to include terminals P-P, MOS transistors MN-MNin diode connection, protection diode circuits HD-HD, MOS transistors T-Tfor discharging electricity from batteries, a battery voltage detection control circuit and a clamp circuit for overvoltage protection. Each of the MOS transistors T-Tfor discharging electricity from the batteries is connected between each neighboring pair of the terminals P-Pthrough wirings. Each of the MOS transistors MN-MNin diode connection is connected between each neighboring pair of the terminals.

Semiconductor integrated circuit

An ESD tolerance of an LDMOS transistor is improved. An N+ type source layer shaped in a ladder and having a plurality of openings in its center is formed in a surface of a P type base layer using a gate electrode and a resist mask. A P+ type contact layer is formed to be buried in the opening. At that time, a distance from an edge of the opening, that is an edge of the P+ type contact layer, to an edge of the N+ type source layer is set to a predetermined distance. The predetermined distance is equal to a distance at which an HBM+ESD tolerance of the LDMOS transistor, which increases as the distance increases, begins to saturate.

Growing community of inventors

Ora-gun, Japan

Tetsuro Hirano