Tokyo Shibaura Electric Co., Ltd.

Tokyo Shibaura Denki Kabushiki Kaisha

Fujikura Limited

Matsushita Electric Industrial Co., Ltd.

Fujitsu Corporation

Agency of Industrial Science and Technology

The Fujikura Cable Works Limited

Tetsuo Yamaguchi

Haruo Tominaga

Tsuneo Takase

Hiroaki Suzuki

Eiji Masuda

Osamu Kohno

Teruaki Tanaka

Kenichi Koyama

Shuzi Harada

Teruyuki Takayama

Ko Agatsuma

Toshihide Hane

Takashi Saito

Seishi Sasaki

Nobuyuki Sadakata

Hideo Abe

Yasuo Tezuka

Yoshimitsu Ikeno

Mitsuo Aihara

Hidehiro Ochiai

Takeshi Harada

Itaru Todoriki

Kenichi Miyauchi

Shigeo Shihyakugari

Shigemitsu Fukuyama

Tuneo Takase

Katsuyuki Kaiho

Yoshio Ogura

Kazunobu Tsutsumi

Teruyuji Takayama

Shinzi Inoue

The present invention provides a packet transfer system for use in an ATM network, which can realize a high-speed packet transfer by implementing a packet transfer process by hardware and also can enhance the throughput of the packet transfer process implemented by software. This packet transfer system comprises a hardware processing portion, which a memory, a packet assembling portion for causing the memory to store a packet assembled from an ATM cell received from a main circuit or an expansion circuit, a higher layer processing portion for performing higher layer processing portion according to header information sent from the packet assembling portion, and a packet determining/transmitting portion for transmitting a packet, which is determined according to a result of the higher layer processing in the higher layer processing portion as required to undergo packet processing, to an expansion circuit and for transmitting a packet, which is determined according to the result of the higher layer processing as not required to undergo packet processing, in a form of an ATM cell to a main circuit. The packet transfer system may further comprises a software processing portion, which has a second memory, a cell assembling/disassembling portion for assembling the ATM cell received from the expansion circuit into a packet, for causing the second memory to store the assembled packet, for reading the packet stored in the second memory and for transmitting the read packet in the form of an ATM cell to the expansion circuit, a packet processing portion for performing packet processing on a packet, which is received in the second memory, by software.

Packet transfer system

In a data packet switching apparatus for switching a data packet, arriving from a plurality of incoming virtual connections in the form of logically multiplexed cells, to a plurality of outgoing virtual connections, efficient use is made of a buffer under congestion. A required data buffer plane quantity monitoring/calculation circuit calculates the number of required data buffer planes (segments) from the packet length contained in the starting cell data, and a packet reception allow/disallow decision/buffer plane quantity securing circuit compares it with the remaining buffer amount. If the number of required buffer planes is larger than the remaining buffer amount, all cell data belonging to the packet are discarded. If the number of required buffer planes is not larger than the remaining buffer amount, the required buffer is presecured by reducing the remaining buffer amount by an amount equivalent to the number of required buffer planes. In a second aspect of the present invention, a unique transmission number is appended to cell data belonging to the packet whose outgoing virtual connection has been determined, the transmission number remaining appended to the cell data until it is transmitted out. The cell data stored in the buffer is output from the buffer for transmission based on the thus determined outgoing virtual connection and the transmission number.

Data packet switching apparatus

A dip forming apparatus for continuously forming a cast rod includes a furnace for holding molten metal, and a crucible having an open top and a bottom wall. The crucible has a core wire-passing region vertically extending therethrough. The crucible has a hole formed through the bottom wall. A passage connects the furnaces to the core wire-passing region. A device is provided for keeping the molten metal in the furnace at a predetermined level so as to flow the molten metal from the furnace to the core wire-passing region through the passage. A partition wall is disposed in the passage and has a throttling orifice of a predetermined size formed therethrough so as to allow the molten metal to pass therethrough to limit the flow of the molten metal from the furnace to the core wire-passing region. A drive device moves the core wire upwardly at a preselected speed through the hole and the core wire-passing region, so that the molten metal in the core wire-passing region accretes on the core wire to form the cast rod.

Dip forming apparatus for continuously forming cast rod

There is disclosed a bushing for use in an apparatus for continuously passing a core wire through a crucible holding molten metal to accrete the molten metal on the core wire to form a cast rod. The bushing is connected to the crucible for passing the core wire therethrough into the crucible. The bushing is tubular and has an engaging portion for engaging with the core wire passing therethrough. The engaging portion is made of ceramics material containing a major proportion of at least one selected from the group consisting of zirconia, silicon carbide and silicon nitride.

Bushing in continuous casting dip forming apparatus

An electrode wire for wire electric discharge machining a workpiece at high speed and high accuracy and a process for preparing the same are provided. The electrode wire comprises a core wire made of a copper clad steel wire, 10 to 70% of the sectional area of the copper clad steel wire being occupied by copper, and a copper-zinc alloy layer covering the core wire. The copper-zinc alloy layer is prepared by coating the core wire with zinc by electroplating or hot galvanizing, followed by heating to disperse copper in the zinc layer to convert the same into a copper-zinc alloy layer wherein the concentration of zinc is increased gradually along the radially outward direction. The preferable thickness of the copper-zinc alloy layer ranges from 0.1 to 15 microns and the average concentration of zinc in the copper-zinc alloy layer is preferably less than 50% by weight but not less than 10% by weight.

Electrode wire for use in electric discharge machining and process for

A forced-cooled superconductor wherein a plurality of superconducting wires are placed within a hollow stabilizer of substantially rectangular section; and a first passage for passing a coolant is longitudinally formed between the stabilizer and a casing encasing the stabilizer, the stabilizer having a plurality of second passages formed therethrough for flowing the coolant from the first passage to the inside of the stabilizer so that the coolant flows through the second passages into the space defined between the superconducting wires for direct cooling. The stabilizer includes a pair of channel members opposedly fitted together to form into a substantially rectangular tube.

Forced-cooled superconductor

Disclosed is a musical envelope control device which is used in an electronic watch with a melody alarm function. The musical envelope control device comprises a memory which stores musical performance data representing pitches and durations of notes; an address counter; a pitch divider which receives pitch data and generates a tone signal in correspondence with the pitch data; a note control circuit which receives note duration data, divides the duration into a preset number of components and then generates a coded signal of a predetermined bit length for each duration component; an envelope decoder which is connected to the note control circuit and converts the coded signals to voltage signals in accordance with a predetermined conversion mode corresponding to a desired envelope waveform; and an envelope control circuit which produces a sound pressure signal having a stepped waveform in response to the voltage signal and which generates a sound signal by synthesizing the sound pressure signal and the tone signal.

Musical envelope control device

Disclosed is a musical envelope-producing device which may be employed for an electronic watch with a melody performance function. The musical envelope-producing device has a memory which stores musical performance data representing pitches and durations of notes; an address counter; a pitch divider which generates a frequency signal corresponding to the pitch data; a note control circuit which divides a duration corresponding to the duration data into eight time components and generates a predetermined division signal when the duration has elapsed; and an envelope circuit which produces a sound pressure signal which is sequentially attenuated in a stepped manner in response to the division signal and which synthesizes the sound pressure signal and the frequency signal.

Musical envelope-producing device

There are provided a frequency divider for dividing the frequency of the frequency signal produced by an oscillator, a counter for counting the number of the frequency divided fundamental signal, an input circuit for prestoring a time to be announced in a memory device so as to operate an alarm device, a comparator for comparing the time counted by the counter with a preset time, an input circuit supplied with a message so as to display the message concurrently with the operation of the alarm device, a character memory device for storing the applied message, and a display device for displaying the stored message. The content of the counter is compared with the time to be announced preset in the memory device. When a coincidence holds a buzzer is operated and at the same time a predetermined message preset in the character memory device is displayed on the display device.

Electronic watches

A time data processing circuit for an electronic timepiece comprises a common line; a signal generator for generating time data signal and first, second, third and fourth control signals; first and second shift register circuits; an arithmetic operation circuit for processing the time data signal and the output signal of the first shift register circuit; a first input/output circuit for coupling, in response to the first control signal, the output terminal of the arithmetic operation circuit to the common line and the input terminal of the first shift register circuit and coupling, in response to the second control signal, the common line to the input terminal of the first shift register circuit; and a second input/output circuit for coupling, in response to the third control signal, the output terminal of the second shift register circuit to the input terminal of the second shift register circuit and the common line and coupling, in response to the fourth control signal, the input terminal of the second shift register circuit to the common line.

Time data processing circuit for electronic timepiece

Disclosed is a data display circuit which comprises a shift register circuit including six cascade-connected shift registers shifting serial data to produce parallel data, a decoder circuit including three decoders receiving the parallel data from the shift register circuit and producing output data corresponding to such input data, a latch circuit coupled to the decoder circuit, a control circuit coupled to the decoder circuit and the latch circuit and supplying these decoder and latch circuits with control pulses so that output data from the decoder circuit may be held temporarily in the latch circuit, and a display device for displaying output data from the latch circuit. In this data display circuit, the three decoders have input terminals coupled respectively with the output terminals of different groups of four cascade-connected shift registers of the shift register circuit, and the control circuit energizes the three decoders at different times, thereby applying substantially the same data from the shift registers to the decoders.

Display circuit

A chronograph includes a reference time counter for measuring a reference time upon receipt of a reference pulse, a plurality of short time counters for measuring a short time difference occurring between runners upon receipt of the reference pulse, a reference pulse control circuit for controlling the supply of the reference pulse to these counters, and an addition circuit for adding the contents of the reference counter to those of the short time counters successively in response to each addition command. The reference pulse control circuit selects either of the reference counter and the short time counters successively in response to each operation of a first switch of a time measuring operator and further supplies the reference pulse to only the selected counter. The reference time counter stores the resultant time resulting from the addition made responsive to each addition command through the operation of a second switch by a single time measuring operator. The resultant time is sequentially displayed through a display circuit so that a single operator can measure the times of a plurality of runners.

Chronograph

A method for producing hollow superconducting cable comprises steps of providing grooves on the outer periphery of a hollow conductor adapted to be engageable therewithin fine multi-filamentary superconductors formed beforehand to be fitted into said grooves, and of fixing securely said multi-filamentary superconductors into said grooves by soldering with a metal having a low melting point.

Method for producing hollow superconducting cables

An integrated circuit includes an input terminal to which a '1,' 'float' and '0' level input signals are selectively supplied; a clock pulse generator for generating a second clock pulse during the high level period of a first clock pulse and a third clock pulse during the low level period of the first clock pulse, and first and second latch circuits operated in response to the second and third clock pulses, respectively, of the clock pulse generator. The input terminal is connected through a resistor to the output of the first clock pulse. The input terminal is also connected to the inputs of the first and second latch circuits. The integrated circuit generates three kinds of outputs whose logical states correspond to different levels of three input signals, respectively, which are selectively supplied to said input terminal.

Integrated circuit having one-input terminal with selectively varying

An optical reader capable of optically reading a plurality of data comprises an object to be read having different coded information placed thereon, with each information having a unique control code, scan means for producing scanning light to be projected to said object, photo-electric conversion means for converting scattered light produced by the scan to an electrical signal, means for determining said control code and information by said electrical signal and means for sorting the information by said control code for storage, whereby different information is optically read while it is sorted by the control code unique to the respective information and stored.

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Yokohama, Japan

Tetsuo Yamaguchi