Mitsubishi Denki Kabushiki Kaisha

Vlsi Technology Research Association

Tetsuo Tada

Ryouichi Takagi

Ryoichi Takagi

Koji Tanaka

Hideshi Maeno

Masanobu Kohara

Hiroshi Noda

Hideo Matsui

Keisuke Okada

Toshiyuki Tsujii

Masahiko Hyozo

Mikio Asai

Keiichi Sawada

Tsuyoshi Yamada

A bare chip (1) is rectangular, and has a front surface (1a) on the center of which semiconductor elements are integrated and a back surface. Notches (2) are formed on a side of the bare chip (1) according to the kind of the semiconductor elements integrated on the bare chip (1). The notches (2) are oblong and extend through the bare chip (1) from the front surface (1a) to the back surface. For example, assuming that the notch (2) represents '1' and a portion without the notch (2) represents '0', one-bit information is obtained according to the presence or absence of the notch (2). When detection of several portions is made, binary information according to a detection result, i.e., information regarding the type of the bare chip (1), is obtained. For detection of the presence or absence of the notch (2), the bare chip (1) is irradiated with light, and then whether the light goes through the notch (2) or is intercepted by the bare chip (1) is detected. Thus, a semiconductor device which allows easy identification of its type is provided.

Semiconductor device with identification function

A method of testing a semiconductor device operating according to predetermined testing information. An output signal of the semiconductor device is received through a signal transmission line and a reference voltage is generated in accordance with an expected logical level of the output signal. The reference voltage is compared with a voltage of the output signal thus received and a current flow is supplied to the signal transmission line in accordance with the result. A logical level of the output signal thus received is determined and a decision is made whether the semiconductor device operates correctly.

Method for testing semiconductor device

A semiconductor testing apparatus includes a comparator for receiving a signal output to a pin terminal of a semiconductor device under test through a transmission line and determining a logical level of the received signal. Semiconductor testing apparatus 1 further includes a current supply circuit for comparing a voltage of an input terminal of comparator with a reference voltage applied by reference voltage sources and supplying a current to transmission line. When a signal ringing on transmission line and a reflection with undershoot and overshoot at input terminal occur, current supply circuit supplies a current to transmission line in accordance with a relationship of magnitude between the voltage at input terminal and the reference voltage. The current supply to transmission line is made to inhibit the overshoot and undershoot of the signal. This allows comparator to carry out a functional testing and a measurement of DC/AC characteristics of a semiconductor device at precise timing and at high speed.

Apparatus and method for testing semiconductor device

A test apparatus for a semiconductor device is provided to be used for testing, wafer by wafer, a semiconductor device formed on a semiconductor wafer. The test apparatus for a semiconductor device comprises a test head, a probe card and a selection circuit. The probe card has an insulating transparent base plate, and protruding parts are formed on the main surface of the base plate corresponding to electrode pads on a test object semiconductor wafer, and conductive layer forming a prober for the electrode pad is formed on the surface of each of these protruding parts. A wiring layer is formed on the surface opposite to the main surface. The wiring layer and the probers are connected electrically through the through holes provided on the base plate. A prober to be connected to the test head is switched electrically, which makes it possible to test a semiconductor device without moving the corresponding semiconductor wafer.

Probe plate used for testing a semiconductor device, and a test

A probing card for wafer testing has a plurality of probes arranged so as to correspond to and come in contact with a plurality of bonding pads of semiconductor devices fabricated on a semiconductor wafer. The probing card comprises a base plate, contact fingers and wiring sections. The base plate is formed of photosensitive glass. The base plate defines through holes extending from one of its main surfaces to the other. The contact fingers are formed as columnar elements filling the through holes and having a cross-sectional area decreasing from opposite ends to an intermediate position thereof. Each contact finger has one end thereof projecting from one of the main surfaces of the base plate. This projecting end of each contact finger at least defines a substantially planar end face. The wiring sections comprise conductive layers formed in a predetermined pattern on the other main surface of the base plate and connected respectively to the other ends of the contact fingers. The through holes are formed in the photosensitive glass base plate by photolithography. The contact fingers may be positioned with high precision relative to a plurality of bonding pads. A stable contact is secured between the bonding pads and contact fingers.

Method of manufacturing a probing card for wafer testing

Probing card for wafer testing and method of manufacturing the same

A probing plate for wafer testing is provided with a plurality of probes arranged so as to correspond to a plurality of bonding pads of semiconductor devices fabricated on a semiconductor wafer. The probing plate has a base plate formed of an insulating material, such as a photosensitive glass, and has contact fingers each having a raised portion in the free end thereof, contact conductors respectively formed on the surfaces of the raised portions of the contact fingers so as to be brought into contact with the corresponding bonding pads, and wiring conductors formed in a predetermined pattern on the surface of the base plate so as to extend respectively from the contact conductors. The contact conductors and the wiring conductors are formed simultaneously by a photolithographic process. The contact fingers and the raised portions thereof are also formed by subjecting the base plate to a photolithographic process. Forming the contact conductors over the surfaces of the raised portions of the contact fingers prevents accidental contact of the contact conductors with the bonding pads of semiconductor devices other than the objective semiconductor devices.

Probing plate for wafer testing

A semiconductor test system comprises an expected value storage area for storing expected values of output data supplied from a semiconductor device under test, a memory device for storing output data directly supplied from the semiconductor device under test in the form of the identical code with that of the expected value storage area, and a comparator for comparing output data from the memory device directly with expected values from the expected value storage area without any conversion.

Semiconductor test system

In a test assist circuit for a semiconductor device, an address input selector (14a) is so switched that an external address signal is supplied to an address decoder (4) to address a memory circuit (3), while an input data selector (14b) is so switched that external input data is stored in an input data register (5), to be stored in addressed memory elements. Information of the most significant bit of the input data register is stored in an input data information storage area (16), and information of the least significant bit of the address decoder is stored in an address decoder information storage area (15). Data read from the memory circuit is stored in an output data register (6), to be outputted to a data output terminal (9) with the information stored in the address decoder information storage area and that stored in the input data information storage area respectively. Thus, the input data information and the address decoder information added to the outputted data are so observed that a determination can be easily made as to whether the memory circuit is in failure or the test assist circuit is in failure, even if the data read from the memory circuit is in failure.

Test assist circuit for a semiconductor device providing fault isolation

A semiconductor test device including a function test algorithmic pattern generator which comprises: an ALU unit with shift-in function for conducting a predetermined arithmetical and logical operation against the base data or the output of an ALU output register; the ALU output register being designed to store the output of the ALU and output a function test algorithmic pattern; and a parity detection circuit which conducts a parity detection against an arbitrary group of bits of the ALU output register, and the detection output is input into a shift-in input of the ALU.

Semiconductor test device

A semiconductor device tester comprises a random data generator, an algorithmic data generator, and a serial data generator. The test data pattern of the data generators are selected and combined to produce test pattern data actually applied to a device under test. At least part of the test data pattern from the algorithmic data generator are applied to one of the random data generator and the serial data generator, which, responsive thereto, produces the random test pattern data or the serial test pattern data.

Semiconductor device tester

A connection of each of the terminals of a semiconductor device under test (DUT) with a test signal provided from a tester and a connection of each of the above stated terminals with a power supply system in the tester are selected in an arbitrary manner based on the serial data for designating connections provided from the tester.

Testing apparatus for semiconductor device

A wafer testing device in which a plurality of wafers can be tested simultaneously significantly reducing the time required for testing each chip. A prober is provided which receives a wafer to be tested. A probe card is coupled to the prober having a window through which a plurality of semiconductor memory chips on the wafer are observable. A plurality of probes are coupled to the periphery of the window in such a manner that the probes can be brought into contact with bonding pads on the plurality of semiconductor memory chips. A tester is connected to the probes which is capable of simultaneously testing each of the plurality of chips.

Semiconductor testing device

A semiconductor device testing device for testing a semiconductor device having input/output terminals includes a dynamic load circuit provided for each of the input/output terminals of the semiconductor device and a comparator provided for each of the input/output terminals of the semiconductor device which compares the voltage value obtained at the input/output terminal with a predetermined value to detect whether the internal state of the semiconductor device is a high impedance state or not. The confirmation of the electrical connection between the semiconductor device and the testing device is thereby conducted by the dynamic load circuit and the comparator.

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Hyogo, Japan

Tetsuo Tada