Adv Antest Corporation

Tetsuo Sotome

Takayuki Nakajima

Kazuhiro Shimawaki

Noboru Akiyama

Mishio Hayashi

Kazutaka Osawa

Toshiro Takahashi

Kouichi Shiroyama

Bit error measurement system

A bit error measurement apparatus is capable of easily specifying pattern conditions which cause bit errors in an incoming signal pattern without measuring all of a test pattern by measuring a bit error rate at a selected position or region of a test pattern. The bit error measurement apparatus includes a test pattern generator which generates the test pattern for verifying the incoming signal to be tested, a verifier which receives the incoming signal and the test pattern and generates a bit error detection signal when the incoming signal and the test pattern disagree, a pattern position detector which detects a measurement region of the test pattern when receiving a synchronizing signal from the test pattern generator and generates a count enable signal corresponding to the detected measurement region, and an error counter which counts the bit error detection signal from the verifier based on the count enable signal from the pattern position detector.

Bit error rate measurement apparatus

An Nth one of N parallel sequences of low-speed data demultiplexed by a demultiplexer from high-speed input data in synchronization with a high-speed clock is compared by N comparators with N parallel sequences of reference patterns. The N parallel sequences of reference patterns are each generated in synchronization with a frequency divided clock obtained by frequency dividing the high-speed clock into 1/N. When any of the comparators provides a disagreement output at least once, one clock pulse is eliminated by a post-clock eliminating circuit from the divided clock so that the N sequences of reference patterns are each delayed by one bit. When a counter detects that any one of the comparators does not provide the disagreement signal for n consecutive bits, the sequence of reference patterns corresponding to this comparator and the Nth sequence of low-speed data are in synchronization with each other. Clock pulses of the number corresponding to the line position of the synchronized sequence of reference patterns are eliminated by a pre-clock eliminating circuit from the high-speed clock which is applied to the demultiplexer. By this, line positions of the N parallel sequences of low-speed data are sequentially shifted so that the Nth sequence of low-speed data assumes the same line position as that of the synchronized reference pattern, and as a result, the N parallel sequences of low-speed data are synchronized with the N parallel sequences of reference patterns, respectively.

Pattern synchronizing circuit

Frequency division circuits in n stages sequentially 1/2-frequency-divide an input clock signal. Pattern generating circuit generates and issues a plurality of pattern data parallel to each other in synchronism with a frequency-divided clock from the final frequency division stage thereof. Multiplexing circuits in n stages are given a plurality of pattern data and multiplex input pattern data in each stage for each two data. Output clock signals of the n-th through first stage frequency division circuits are supplied to the first through n-th multiplexing circuits via respective delay circuits as multiplexing control clock signals. A retiming circuit is inserted in series to the input of at least one of the multiplexing circuits, and a multiplexing control clock signal applied to said one multiplexing circuit from the corresponding frequency division circuit is given to the retiming circuit as a retiming clock signal. A phase switching circuit is inserted in series to the output of the frequency division circuit which applies the multiplexing control clock signal to said one multiplexing circuit. When a node of the input pattern data in the retiming circuit approaches the edge of a retiming clock signal within a predetermined range, an approach detection signal is issued from the approach detection circuit. The phase switching circuit shifts the phase of the input clock signal in response to the approach detection signal by a predetermined quantity and issues the phase-shifted clock signal.

High-rate pulse pattern generator

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Tatebayashi, Japan

Tetsuo Sotome