Hitachi, Ltd.

Hitachi Software Engineering Company, Ltd.

Hitachi Information Technology Co., Ltd.

Tetsuo Sasaki

Tatsuki Ishii

Yousuke Nagao

Hiroyuki Suzuki

Katsuyoshi Suzuki

Katsuyuki Itoh

Hachidai Nagase

Toshiaki Okada

Katsuyuki Itou

Tooru Hiyama

Misao Takimoto

Ippei Hachiya

Itaru Matsumoto

A wiring route deciding system, for a wiring board containing a multi-pin part, includes an input unit for receiving wiring board and wire connection information, wiring constraint information and wiring setting information, for example. The system further contains a draw wiring processing unit which decides a wiring route of a draw wiring from a part pin to a part periphery boundary based on wiring information inputted by the input unit, an inter-draw wire wiring processing unit which decides the wiring route taken between end points of the draw wiring decided by the draw wiring processing unit, and an output unit which outputs a wiring route information based on that decided by both the draw wiring processing unit and the inter-draw wire wiring processing unit. There is also provided a method counterpart for a wire routing scheme for a wiring board containing a multi-pin part.

Method and system for deciding a wiring route

A wiring design system when applied to wiring boards having various wiring restrictions, has a rough wiring plan at the floor plan stage so as to complete a wiring design satisfying the wiring restrictions in a short period of time while evaluating the congestion degree of the wiring. Logical connection information for wiring parts and signal group information for handling the connection information is input as a signal group. The signal group is handled as a wiring unit for a wiring path search and the signal group is divided into smaller groups. An optimum path is then determined in such a way that the divided smaller groups run adjacent to one another whenever appropriate.

Wiring design method and system for electronic wiring boards

Each flip-flop-to-flip-flop path delay and a target machine cycle obtained in the stages of physical design and packaging design are used as input, and with respect to a path in which the path delay is not less than the target machine cycle, a closed loop including the path is extracted, and the timing of a clock signal of each flip-flop is adjusted so as to permit data transmission along the closed loop in a required cycle-number. At this time, a path along which data transmission is impossible in the target machine cycle or a closed loop including the path is listed in order to be modified. As methods of supplying a clock signal to each flip-flop, a plurality of methods different in the adjustable range of clock timing are combined and used.

Design method and system for achieving a minimum machine cycle for semiconductor integrated circuits

A control device and a storage device are provided. The storage device has a clock signal file for determining a delay reference value for a path, and a logic information file for holding description of elements in the path. The control device refers to the clock signal file and the logic information file to determine an combination of the emitter-follower current and the value of the current-switch current of a certain element in the path.

System and method for optimizing delays in semiconductor circuits

A method and a system for assisting mending of an LSI after it has been formed into a chip which is necessitated by modification of logic etc. The mending includes corrections by connecting or cutting interconnections of the LSI. The assisting method and system provides a method and a system for detecting which interconnection or connections should be subjected to mending according to the logic modification, or a method and a system for detecting an area or areas where the intended mending can be carried out, or a method and a system for advising a mending-allowable rate of the LSI. This invention further provides a wiring structure suited for mending of the LSI and a wiring method for the same. By this method, a wiring structure which preliminarily has a mending area in preparation for possible modification in logic is produced.

Method and a system for assisting mending of a semiconductor integrated

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Hadano, Japan

Tetsuo Sasaki