Fujitsu Semiconductor Limited

Fujitsu Microelectronics Limited

Fujitsu Corporation

Tetsuo Miyamoto

Toshiya Uchida

Tatsuya Kanda

Tatsushi Otsuka

Shinnosuke Kamata

Ayako Sato

Hidenaga Takahashi

Yoshinobu Yamamoto

Masanori Kurita

Satoru Shirakawa

Takahiko Sato

Hiroyuki Kobayashi

Hitoshi Ikeda

Tomohiro Kawakubo

Syusaku Yamaguchi

Yasuhiro Watanabe

A data transfer control apparatus includes a memory, a write control part controlling data writing to the memory, a read control part controlling data reading from the memory, a read-start calculation part calculating an output timing of a notification which indicates a read-start operation to the read control part based on each transfer condition of the data writing to the memory and the data reading from the memory, and an asynchronous transfer part asynchronously transferring a clock of the notification, and notifying the read control part of the notification.

Data transfer control apparatus and data transfer control method

Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof. A memory device that is operated in response to a command from a memory controller has a plurality of banks that respectively have memory cores including memory cell arrays and decoders and are selected by bank addresses; and a control circuit, which, in response to a background refresh command, causes the memory cores within refresh target banks set by the memory controller to successively execute refresh operation a number of times corresponding to refresh burst length that is set by the memory controller, and, in response to a normal operation command, further causes the memory cores within banks other than the refresh target banks and selected by the bank addresses to execute normal memory operation corresponding to the normal operation command, during the refresh operation executed by the memory cores within the refresh target banks.

Memory device, memory controller and memory system

An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals. Each of the memory unit areas stores therein data of a plurality of bytes or bits corresponding to the plurality of input/output terminals respectively, and the memory cell array and the input/output unit access a plurality of bytes or bits stored in a first memory unit area corresponding to the input address and in a second memory unit area adjacent to the first memory unit on the basis of the input address and combination information of the bytes or bits in response to a first operation code, and then, from the plurality of bytes or bits within the accessed first and second memory unit areas, associate a combination of the plurality of bytes or bits based on the combination information, with the plurality of input/output terminals.

The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.

An arbiter circuit includes a priority coefficient calculating unit, a priority coefficient comparator an acceptance determining unit, and a priority determining unit. The priority coefficient calculating unit calculates for each request an arbitration priority coefficient based on a priority level set for each request by requesters. The priority coefficient comparator compares arbitration priority coefficients calculated for the requesters by the priority coefficient calculating unit. The acceptance determining unit determines whether to accept the requests based on the comparison result by the priority coefficient comparator. When the arbitration priority coefficient calculated by the priority coefficient calculating unit is equal between two or more requests, the priority determining unit determines a priority order for accepting the requests.

Arbiter circuit

A functional block design method capable of shortening the period needed for developing functional blocks in compliance with orders. A logic design is prepared for a desired number of memory floor plan blocks with respective predetermined data storage capacities and a fixed block different from the memory floor plan blocks, and block-based design data is created in compliance with the logic design. The created block-based design data is verified in that a constraint on the creation of a CPU macro is always fulfilled within the limits up to which the memory blocks can be mounted. Using the verified block-based design data, design data of a CPU macro functional block in which a desired number of memory blocks corresponding to a desired memory capacity are connected to the fixed block is generated.

Functional block design method and apparatus

An integrated circuit layout method for placing a plurality of cells within a chip comprises a process for sorting the plurality of cells (or function macros) that are to be laid out in order of their delay times (or operation speed margins for macro), placing cells (or macros) having the largest delay times (or smallest speed margin for macro) closer to the peripheral area of the chip, and as the cell delay times get smaller(or the speed margins get larger), placing the relevant cells (or macros) closer to the central area of the chip.

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Kawasaki, Japan

Tetsuo Miyamoto