Kabushiki Kaisha Toshiba

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International Business Machines Corporation

Ebara Corporation

Tetsuo Matsuda

Hisashi Kaneko

Katsuya Okumura

Hiroshi Toyoda

Koji Mishima

Tadashi Iijima

Wataru Saito

Junji Kunisawa

Tokuhisa Ohiwa

Natsuki Makino

Kenichi Tokano

Yoshio Ozawa

Haruo Okano

Katsuhiko Hieda

Kenji Nakamura

Nobuo Hayasaka

Hiroaki Inoue

Kazuyuki Higashi

David M Dobuzinsky

Akihiro Kajita

Seiji Inumiya

Noriaki Matsunaga

Toshiyuki Morita

Takashi Kawanoue

Tomomi Imamura

Yoshinosuke Nishijo

Norio Kimura

Hiroyuki Yano

Gaku Minamihaba

Junichi Wada

Hideki Shibata

Naofumi Nakamura

Manabu Tsujimura

Tsukasa Azuma

Dai Fukushima

Kenya Kobayashi

Toshifumi Nishiguchi

Tadashi Matsuno

Minakshisundaran Balasubramanian Anand

Mitsuko Odagaki

Yosuke Himori

Son Van Nguyen

Koji Hashimoto

Yuichiro Yamazaki

Michael Jay Shapiro

James Gardner Ryan

Motosuke Miyoshi

Yuuichi Mikata

Mizuki Nagai

Iwao Kunishima

Hiroko Nakamura

Hideaki Hirabayashi

Hideki Okumura

Masanobu Tsuchitani

Osamu Nagano

Maria Ronay

Atsuko Yamashita

Ryoichi Kimizuka

Akimichi Yonekura

A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type provided on the first semiconductor region, a third semiconductor region of the first conductivity type provided on the second semiconductor region, a first insulating part provided in the first semiconductor region, a first electrode provided in the first semiconductor region, the first insulating part disposed between the first electrode and the first semiconductor region, a second insulating part provided on the first electrode, a gate electrode provided on the second insulating part, a gate insulating part provided between the gate electrode and the second semiconductor region, and a second electrode provided on the second semiconductor region and on the third semiconductor region, and is electrically connected to the second semiconductor region, the third semiconductor region, and the first electrode.

Method of manufacturing a semiconductor device

Semiconductor device and method of manufacturing the same

A method for manufacturing a semiconductor device, includes: forming a first metal layer on a semiconductor substrate, the semiconductor substrate including a diffusion layer; forming an insulating layer having an opening on the first metal layer; forming a second metal layer on the first metal layer in the opening of the insulating layer; removing the insulating layer; covering an exposed surface of the second metal layer with a third metal layer, the third metal layer including a metal having an ionization tendency lower than that of the second metal layer; and forming an electrode interconnect including the first metal layer, the second metal layer, and the third metal layer by removing the first metal layer using the third metal layer as a mask.

Semiconductor device and method for manufacturing of same

A single crystal semiconductor layer of a first conduction type is disposed on a surface of a semiconductor substrate. A plurality of trenches are provided in the semiconductor layer to form a plurality of first semiconductor regions of the first conduction type at intervals in a direction parallel to the surface. An epitaxial layer is buried in the plurality of trenches to form a plurality of second semiconductor regions of a second conduction type. The plurality of second semiconductor regions each includes an outer portion with a high impurity concentration formed against an inner wall of the trench, and an inner portion with a low impurity concentration formed inner than the outer portion.

Semiconductor device including first and second semiconductor regions with increasing impurity concentrations from a substrate surface

Semiconductor device having trenches filled with a semiconductor having an impurity concentration gradient

Semiconductor device with tapered trenches and impurity concentration gradients

Power semiconductor device with epitaxially-filled trenches

A cathode potential is applied to a conductive layer formed on a substrate having a depression pattern. A plating solution in electrical contact with an anode is supplied to the conductive layer to form a plating film on the conductive layer. At this time, the plating solution is supplied by causing an impregnated member containing the plating solution to face the conductive layer. Since the plating solution stays in the depression, a larger amount of plating solution is supplied than on the upper surface of the substrate, and the plating rate of the plating film in the depression increases. Consequently, the plating film can be preferentially formed in the depression such as a groove or hole.

Plating method

A first semiconductor pillar layer of a first conductivity type is formed on a main surface of a semiconductor substrate of the first conductivity type. A second semiconductor pillar layer of a second conductivity type is formed adjacent to the first semiconductor pillar layer. A third semiconductor pillar layer of the first conductivity type is formed adjacent to the second semiconductor pillar layer. A semiconductor base layer of the second conductivity type is formed on the main surface of the second semiconductor pillar layer. An insulated-gate type semiconductor element is formed in the semiconductor base layer. The carrier concentration on the side of a main surface of each of said first through third semiconductor pillar layers is higher than a carrier concentration on the opposite side of said main surface in each of said first through third semiconductor pillar layers.

A plating method and apparatus for a substrate fills a metal, e.g., copper, into a fine interconnection pattern formed in a semiconductor substrate. The apparatus has a substrate holding portionhorizontally holding and rotating a substrate with its surface to be plated facing upward. A seal materialcontacts a peripheral edge portion of the surface, sealing the portion in a watertight manner. A cathode electrodepasses an electric current upon contact with the substrate. A cathode portionrotates integrally with the substrate holding portionAn electrode arm portionis above the cathode portionand movable horizontally and vertically and has an anodeface-down. Plating liquid is poured into a space between the surface to be plated and the anodebrought close to the surface to be plated. Thus, plating treatment and treatments incidental thereto can be performed by a single unit.

Method of performing electrolytic treatment on a conductive layer of a substrate

Disclosed is a method of manufacturing an electronic device, comprising forming a concave portion on the surface of a base member, forming an electrically conductive seed layer on that surface of the base member on which a plated film is to be formed, and applying an electrolytic plating treatment with the seed layer used as a common electrode under the condition that a substance for accelerating the electrolytic plating is allowed to be present in the concave portion of the base member in an amount larger than that on the surface of the base member to form a plated film.

Method of manufacturing electronic device

An electronic device manufacturing method comprises forming an insulating film above a substrate, forming a to-be-filled region which includes at least one of an interconnection groove and a hole in the insulating film, forming a first conductive film containing a catalyst metal which accelerates electroless plating, so as to line an internal surface of the to-be-filled region, forming a second conductive film on the first conductive film by the electroless plating, so as to line the internal surface of the to-be-filled region via the first conductive film, and forming a third conductive film on the second conductive film by electroplating, so as to fill the to-be-filled region via the first conductive film and the second conductive film.

Electronic device manufacturing method

Plating method and plating apparatus

Growing community of inventors

Tano-gun, Japan

Tetsuo Matsuda