Sanyo Semiconductor Co., Ltd.

Sanyo Electric Co., Ltd.

Semiconductor Components Industries, LLC

Tetsuo Kosuge

Naoki Tanahashi

Kensuke Fujimura

When data is an HDTV signal, a buffer memory is used as two banks and pipeline processing is performed. When data is an SDTV signal, on the other hand, the buffer memory is used as a bankless buffer memory, and the pipeline processing is not performed.

TV signal processing circuit

A data storage/reading circuit successively stores frame data in a data storage memory. A start address storage unit memorizes a start address of non-reference frame data stored in the data storage memory. A decoding circuit starts a decoding operation by reading the data from the start address of already stored non-reference frame data, based on a decoding start command.

Decoding circuit

Input bits having a predetermined number of bits are divided into a plurality of bits by a bit dividing apparatus. Several of the divided bits are input into a recording apparatus, and are converted into address information. The data subjected to variable length decoding and a number of bits of the data are output from the recording apparatus according to the output of the recording apparatus. A plurality of kinds of variable length decoding are performed by rewriting the table of the recording apparatus.

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Gunma-ken, Japan

Tetsuo Kosuge