Mitsubishi Denki Kabushiki Kaisha

Tetsuo Katoh

Kiyohiro Furutani

Mikio Asakura

Mitsutomi Yamashita

A test signal generating circuit generates internal test control signals from a small number of signals supplied via an address terminal in a test mode operation. According to the test control signals, the values of internal row address signal bits from an address buffer are set, while a row-related control circuit with test control function controls operations of a row selection circuit and bit line peripheral circuitry according to the test control signals. A plurality of word lines are driven simultaneously into a selected state and an acceleration test is performed according to a small number of control signals in a short period of time. Voltage stress applied between memory cell capacitors and between word lines can be accelerated with a small number of control signals.

Semiconductor memory device capable of correctly and surely effecting voltage stress acceleration

In an SDRAM chip, two signal generation circuits are provided corresponding to two test circuits arranged at either ends of a rectangular semiconductor substrate. Each signal generation circuit is provided in the proximity of corresponding test circuit. Hence, a signal line for test signal can be reduced and smaller chip area can be achieved compared with the conventional case where one signal generation circuit is provided at a center of the semiconductor substrate and a test signal is supplied to two test circuits from the signal generation circuit.

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Hyogo, Japan

Tetsuo Katoh