Mitsubishi Denki Kabushiki Kaisha

Tetsuo Kato

Mikio Asakura

Hideto Hidaka

Kiyohiro Furutani

Takayuki Miyamoto

Tetsushi Tanizaki

Kei Hamade

Tsukasa Ooishi

Takashi Kono

Takeshi Hamamoto

Yasuhiro Konishi

Yasuhiko Taito

Shigehiro Kuge

By devising the arrangement of memory arrays surrounding the central region of the chip, the total length of a data bus can be reduced. The memory arrays are arranged such that one of two memory arrays that are located at the positions point-symmetric with respect to the central region corresponds to lower DQ terminals, and the other memory array corresponds to upper DQ terminals. Preferably, the memory arrays corresponding to the upper DQ terminals and the memory arrays corresponding to the lower DQ terminals are each located collectively. Thus, a semiconductor memory device with improved data propagation characteristics on the data bus can be provided.

Semiconductor memory device with improved data propagation characteristics of a data bus

A circuit generating a test mode instructing signal includes a test mode register circuit which is set to a state disabling instruction of a test mode in a standby state. An intended test mode can be accurately selected even when the test mode is instructed in accordance with a plurality of external signals varied in timing from each other. A semiconductor device allows accurate and efficient execution of the test without requiring increase in area occupied by an array.

Semiconductor device operable in a plurality of test operation modes

Internal parameter control signal generating units generate internal parameter control signals for adjusting internal parameters of a semiconductor memory device. Each internal parameter control signal generating unit includes an anti-fuse element formed with a data holding capacitor of a memory cell. The anti-fuse element is blown with application of a high voltage according to a parameter adjustment signal to break down a dielectric film and then, act as a resistance element. The internal parameter control signal generating unit sets a signal level of a corresponding internal parameter control signal in a non-volatile manner according to the presence or absence of a blowing input to the anti-fuse element.

Semiconductor memory device capable of adjusting internal parameter

A semiconductor memory device includes a first test row decoder ( ) for selecting memory cells in normal rows in a test mode, a second test row decoder ( ) for selecting spare memory cell rows, a first test column decoder ( ) for selecting memory cells in normal columns, and a second test column decoder ( ) for selecting spare memory cell columns. A control circuit ( ) may perform switching between four combinations of the row and column decoders by using a control signal (SRT) and a control signal (SCT). All spare memory cells are tested prior to reparation of a defective memory cell for yield enhancement.

Semiconductor memory device and method of checking same for defect

A semiconductor memory device according to the present invention includes: a test mode setting circuit capable of serially setting a plurality of test modes in accordance with an external signal; a voltage generating circuit; a column related control circuit; a row related control circuit; and a memory cell array. In a corresponding test mode, odd-numbered word lines/even-numbered word lines are brought into a selection/non-selection state. In the corresponding test mode, a voltage of the bit line is set higher (an internal power supply voltage) or lower (a ground voltage) than an equalization voltage in a normal operation mode. Thus, a checker pattern can efficiently be written.

Semiconductor memory device having a test mode setting circuit

Data are read out from sub-arrays within a memory cell array in batches. A data bus driving circuit compares the read data, and, according to the comparison result, drives the potentials of data buses with small amplitudes. A data retaining circuit retains fail information indicating the presence of a fail bit, according to the data on the data buses. The data retaining circuit responds to an externally supplied designation, and provides a pass/fail information output circuit with the fail information with large amplitude. The fail information is further output to the outside.

Semiconductor integrated circuit device tested in batches

A semiconductor memory device includes a first test row decoder (,) for selecting memory cells in normal rows in a test mode, a second test row decoder (,) for selecting spare memory cell rows, a first test column decoder (,) for selecting memory cells in normal columns, and a second test column decoder (,) for selecting spare memory cell columns. A control circuit (,) may perform switching between four combinations of the row and column decoders by using a control signal (SRT) and a control signal (SCT). All spare memory cells are tested prior to reparation of a defective memory cell for yield enhancement.

A semiconductor device according to the present invention includes a plurality of test mode circuits. Each test mode circuit includes a plurality of decode circuits decoding an input signal and a plurality of latch circuits. Each decode circuit generates a test mode signal. The test mode signals are held in the latch circuits. Each test mode circuit further includes decode circuits outputting a group reset signal for resetting a corresponding latch circuit. Thus, a plurality of test mode signals can be combined arbitrarily and serially.

Semiconductor device having test function

A semiconductor memory device includes a first test row decoder (9a) for selecting memory cells in normal rows in a test mode, a second test row decoder (9b) for selecting spare memory cell rows, a first test column decoder (10a) for selecting memory cells in normal columns, and a second test column decoder (10b) for selecting spare memory cell columns. A control circuit (11) may perform switching between four combinations of the row and column decoders by using a control signal (SRT) and a control signal (SCT). All spare memory cells are tested prior to reparation of a defective memory cell for yield enhancement.

In a semiconductor memory device, a self refresh cycle program circuit is provided and a refresh operation is conducted in accordance with one of the refresh cycles programmed in the refresh-cycle program circuit. The refresh cycle of the self-refresh mode is selected from a plurality of refresh-cycle types. A plurality of refresh modes allows a refresh cycle to be selected from a plurality of refresh-cycle types in accordance with a selected refresh mode.

Semiconductor memory device having a refresh-cycle program circuit

Two NAND gates are provided corresponding to each of a plurality of pads. By connecting a mode switching pad to power supply potential or ground potential, one of the two NAND gates provided corresponding to each pad is activated, and the other NAND gate is non-activated. As a result, different mode select signals are provided from the output of each NAND gate.

Mode setting circuit of semiconductor device

In a dynamic random access memory device, first, second and third switches and an internal signal generator therefor are provided besides circuit portions of an ordinary random access memory such as a memory cell. A data input circuit includes data input pins for receiving an input data and data-in-buffers for storing the input data. The first switch can connect one of data input pins to either one of data in buffers or an end of a signal line. The second switch can connect the data-in-buffers to a data output circuit. The third switch can connect the internal voltage supply line to either an internal voltage generator or the other end of the signal line. When a memory is tested, the switch signal generator generates signals so as to make the first switch connect the one of said input pins to the end of the signal line, to make the second switch to connect the data in buffer to the data output circuit, and to make the third switch to connect an internal voltage supply line to the other end of the signal line. Thus, an external voltage can be supplied through one of the data input pins instead of an internal voltage generator, and defective products can be selected out. In an alternative example, the first switch is provided for the data output pins instead of the data input pins.

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Hyogo, Japan

Tetsuo Kato