Hitachi, Ltd.

Renesas Electronics Corporation

Renesas Technology Corp.

Hitachi Ulsi Engineering Corp.

Tetsuo Iijima

Isao Yoshida

Akira Mishima

Takuro Kanazawa

Norio Kido

Katsuo Ishizaka

Kentaro Ochi

Takeaki Okabe

Kazutoshi Ashikawa

Mitsuo Ito

Atsushi Fujiki

Masatoshi Nakasu

Minoru Suda

Katuo Ishizaka

Masayoshi Kobayashi

Kozo Sakamoto

Shigeo Ohtaka

Shigeo Otaka

Hideki Tsunoda

Harutora Shono

Ken Uchid

Akio Andoo

A semiconductor device formed by using semiconductor packages is provided. The semiconductor device includes two semiconductor packages adjacently arranged in opposite directions on an inductive conductor. Terminals of the two semiconductor packages are joined by a third lead. The third lead is arranged substantially in parallel to the inductive conductor. Leads at the joint portions have, for example, a bent structure, and the third lead is arranged to be close to the inductive conductor.

Semiconductor device for power conversion

A semiconductor device formed by using semiconductor packages is provided. The semiconductor device includes two semiconductor packages adjacently arranged in opposite directions on an inductive conductor. Terminals of the two semiconductor packages are joined by a third lead. the third lead is arranged substantially in parallel to the inductive conductor. Leads at the joint portions have, for example, a bent structure, and the third lead is arranged to be close to the inductive conductor.

Semiconductor device

A power MOSFET Qp and a protection circuitare formed over a semiconductor substrate to constitute a construction in which the power MOSFET Qp and the protection circuitare electrically separated from each other. Then, a screening voltage is applied between the gate electrode and the source electrode of the power MOSFET Qp which is electrically separated from the protection circuit, thereby eliminating a power MOSFET Qp having a latent defect. Subsequently, a non-defective power MOSFET Qp and the protection circuitare electrically connected by a bonding wire.

Semiconductor integrated circuit device, and method of manufacturing the same

ON resistance and leakage current of a vertical power MOSFET are to be diminished. In a vertical high breakdown voltage MOSFET with unit MOSFETs (cells) arranged longitudinally and transversely over a main surface of a semiconductor substrate, the cells are made quadrangular in shape, and in each of the cells, source regions whose inner end portions are exposed to the interior of a quadrangular source contact hole are arranged separately and correspondingly to each side of the quadrangle. Each source region is trapezoidal in shape, and a lower side of the trapezoid is positioned below a gate electrode (gate insulating film), while an upper side portion of the trapezoid is exposed to the interior of the source contact hole. The four source regions are separated from one another by diagonal regions of the quadrangle.

A power MOSFET Qp and a protection circuit,are formed over a semiconductor substrate to constitute a construction in which the power MOSFET Qp and the protection circuit,are electrically separated from each other. Then, a screening voltage is applied between the gate electrode and the source electrode of the power MOSFET Qp which is electrically separated from the protection circuit,, thereby eliminating a power MOSFET Qp having a latent defect. Subsequently, a non-defective power MOSFET Qp and the protection circuit,are electrically connected by a bonding wire.

An improvement in conditions that protective functions of an insulated gate semiconductor device with a protection circuit incorporated therein are performed, an improvement in the cutoff of heating, the prevention of malfunctions and an improvement in ease of usage can be achieved. The insulated gate semiconductor device of the present invention comprises a power insulated gate semiconductor element (M9), at least one MOSFET (M1 through M7) for a protection circuit, for controlling the power insulated gate semiconductor element, a constant-voltage circuit using forward voltages developed across diodes (D2a through D2f) for the constant-voltage circuit, and voltage restricting diodes (D1 and D0a through D0d) for controlling the upper limit of a power supply voltage of the constant-voltage circuit. Power to be supplied to the voltage restricting diodes is supplied from an external gate terminal of the power insulated gate semiconductor element. The present invention can bring about an advantageous effect that an improvement in reliability of the insulated gate semiconductor device and an improvement in the ease of use can be achieved.

Insulated gate semiconductor device and driving circuit device and

A power transistor device is provided which has a function of clamping the collector voltage to a stable level for a wide range of temperature variations. In the power transistor device, a plurality of pn junctions are formed to fabricate Zener diodes in the polycrystalline silicon film in the form of rings. The ring configuration of the Zener diodes eliminates an end at the pn junction and prevents the junction surface from being exposed, making it possible to use as a stable Zener voltage the dielectric strength characteristic of the pn junction having a very small temperature coefficient.

Power transistor device having collector voltage clamped to stable level

In a transistor where collector is connected to an inductive load and switching current flows, a Zener diode comprising structure of plural pn-junctions constituted in series form to a polysilicon is provided between collector and base. Further MOSFET is switch-controlled by control voltage formed based on Zener current flowing through the Zener diode, and current path in parallel form to the Zener diode is constituted. Since temperature characteristic coefficient of a Zener diode formed in a polysilicon film is very small, the reverse voltage generated in the inductive load can be set to stable voltage in spite of the temperature variation. Further the MOSFET is provided in parallel form, thereby relatively large ON-resistance value of the Zener diode can be decreased.

Power transistor device including power transistors in darlington

A semiconductor device has a semiconductor substrate, an insulated gate field-effect transistor section formed in the substrate and a peripheral section formed in the substrate and arranged to substantially surround the field-effect transistor section. A passivation layer of an organic material is provided over that part of the substrate in which the field-effect transistor section is not located. The device may be resin mold packaged for an enhanced humidity-resistance by making use of the fact tht the peripheral portion of the device is covered with organic resin.

Method of manufacturing semiconductor device with controlled carrier

An insulated gate semiconductor device contains a protective element for protecting the gate electrode of an insulated gate field effect transistor. The protective element is formed of the same semiconductor layer as that of the gate electrode of the insulated gate field effect transistor and is formed integrally with the gate electrode on an insulating film formed on the surface of a semiconductor substrate.

Insulated gate semiconductor device with back-to-back diodes

A method for fabrication a vertical MOSFET which contains a protective element for protecting the gate electrode of an insulated gate field effect transistor. The protective element is formed of the same semiconductor layer as that of the gate electrode of the insulated gate field effect transistor and is formed integrally with the gate electrode on an insulating film formed on the surface of a semiconductor substrate.

Growing community of inventors

Maebashi, Japan

Tetsuo Iijima