Nippondenso Co., Ltd.

Tetsuo Hirano

Hiroaki Tanaka

Ryuichirou Abe

Takahiro Yanagi

A differential amplifier circuit whose noise is reduced when used in a CMOS operational amplifier without increasing its cost includes a differential input stage circuit in which gate lengths of load transistors and gate lengths of differential input transistors are set to an optimal ratio to minimize internal transistor noise components.

Differential amplifier circuit having low noise input transistors

A switched capacitor circuit includes a capacitor, a MOS switch and a timing generating circuit. The MOS switch is connected with the capacitor in series for discharging electric charges which are charged into the capacitor. The MOS switch includes a plurality of MOS transistors which are parallelly connected with each other. The timing generating circuit generates timing signals to the MOS switch so that the MOS transistors are turned on one after another in response to each timing signal. Sampling noise is reduced because an ON-state resistance of the MOS switch is transiently high.

Switched capacitor circuit

Output signals, representing data read out from a memory cell array comprising a plurality of memory cells arranged in a matrix of m rows and n columns, each cell comprising an EPROM transistor, are fed to a sense amplifier. A row of the memory cell array is selected by signals SRl-SRm coming from a row decoder. The output of the selected row is taken out by a column select transistor selected by signals SCl-SCn from a column decoder before being fed to the sense amplifier. The sense amplifier comprises a memory cell output detecting circuit having a first load transistor for receiving output read out from the memory cell array and a dummy cell output detecting circuit having a second load transistor to which dummy cell equivalent to the memory cell is connected. The circuit of the first load transistor and that of the second load transistor form a current mirror circuit. The sense amplifier also comprises a sense amplifier output evaluation circuit having differential amplifiers which transmit output voltages of the memory cell output detecting circuit and of the dummy cell output detecting circuit to reflect the respective currents running through the first and second load transistors.

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Anjo, Japan

Tetsuo Hirano