Kabushiki Kaisha Toshiba

Toshiba Client Solutions Co., Ltd.

Tetsuo Hatakeyama

Takashi Shinohe

Kozo Kinoshita

Johji Nishio

Chiharu Ota

According to one embodiment, a wearable device includes a display, a detector, and a hardware processor. The display displays a screen keyboard on a screen when an instruction is input. The detector includes a polygonal plate and detects a tracing action of a finger over a side of the polygonal plate. The hardware processor determines whether the screen keyboard is displayed on the screen when the detector detects the tracing action, and executes an action on the screen in accordance with the tracing action detected by the detector when the hardware processor determines that the screen keyboard is displayed.

Wearable device and operation method of executing an action on the screen accordance with finger tracing on the side edges of the touch pad

A semiconductor device includes a semiconductor substrate made of silicon carbide and having a surface, a normal vector for the surface having an off angle with respect to a &#x3c;0001&#x3e; direction or a &#x3c;000-1&#x3e; direction, a semiconductor layer of a first conductivity type formed on the semiconductor substrate, a first semiconductor region of a second conductivity type formed in a surface region of the semiconductor layer, a source region of a first conductivity type formed in a surface region of the first semiconductor region, a second semiconductor region of a second conductivity type formed in the surface region of the semiconductor layer, contacting the first semiconductor region, and having a bottom surface lower than a bottom surface of the first semiconductor region, wherein at least one end of the bottom surface of the second semiconductor region is perpendicular to an off angle direction.

Semiconductor device

A semiconductor device includes: a semiconductor substrate; a first conductivity type semiconductor layer that is formed on the substrate and is made of silicon carbide; an active area formed on a surface of the semiconductor layer; a first semiconductor area of a second conductivity type formed on the surface of the semiconductor layer to surround the active area; a second semiconductor area, provided to adjoin an outer side of the first semiconductor area on the surface of the semiconductor layer and surround the first semiconductor area, in which a second conductivity type impurity area having the same impurity concentration and the same depth as those of the first semiconductor area is formed in a mesh shape; a first electrode provided on the active area; and a second electrode provided on the rear surface of the semiconductor substrate.

High-voltage semiconductor device

According to one embodiment, a semiconductor device provided with a structure, which prevents withstand voltage deterioration and may be manufactured at a low cost, is provided. The semiconductor device is provided with a semiconductor substrate, a first conductive type semiconductor layer formed of silicon carbide formed on the substrate, an active region formed on a surface of the semiconductor layer, a second conductive type first semiconductor region formed on the surface of the semiconductor layer so as to surround the active region, a second semiconductor region provided on the surface of the semiconductor layer so as to contact the outside of the first semiconductor region to surround the first semiconductor region in which a second conductive type impurity region having impurity concentration and a depth identical to those of the first semiconductor region is formed into a mesh shape, a first electrode provided on the active region, and a second electrode provided on a backside of the semiconductor substrate.

A semiconductor device includes a semiconductor substrate of a first conductivity type having a top surface and a bottom surface, a semiconductor layer of a first conductivity type formed on the top surface of the semiconductor substrate, and having an active region and an edge termination region surrounding the active region, a first semiconductor region of a second conductivity type formed in the edge termination region adjacent to an edge of the active region, a second semiconductor region of a second conductivity type buried in the edge termination region in a sheet shape or a mesh shape substantially in parallel with a surface of the semiconductor layer, a first electrode formed on the active region of the semiconductor layer and a part of the first semiconductor region, and a second electrode formed on the bottom surface of the semiconductor substrate.

A semiconductor device includes an SiC substrate, a normal direction of the substrate surface being off from a &#x3c;0001&#x3e; or &#x3c;000-1&#x3e; direction in an off direction, an SiC layer formed on the SiC substrate, a junction forming region formed in a substantially central portion of the SiC layer, a junction termination region formed to surround the junction forming region, and including a semiconductor region of a conductivity type different from the SiC layer formed as a substantially quadrangular doughnut ring, having two edges facing each other, each crossing a projection direction, which is obtained when the off direction is projected on the upper surface of the SiC layer, at a right angle, wherein a width of one of the two edges on an upper stream side of the off direction is L, that of the other edge on a down stream side is L, and a relation L&#x3e;Lis satisfied.

An I/O controller to which an I/O device is connected includes a DMA controller (DMAC) and an access control unit (ACU). The DMAC executes DMA transfer in accordance with data transfer control information set in a control/status register by a user process. The ACU limits execution of DMA transfer by the DMAC based on access control information set in a control/status register by a privileged process, and disables the DMAC from accessing any memory area other than the memory area that can be accessed by the user process.

Memory protection during direct memory access

A high-breakdown-voltage semiconductor device comprises a high-resistance semiconductor layer, trenches formed on the surface thereof in a longitudinal plane shape and in parallel, first regions formed on the semiconductor layer to be sandwiched between adjacent ones of the trenches and having an impurity concentration higher than that of the semiconductor layer, a second region having opposite conductivity to the first regions and continuously disposed in a trench sidewall and bottom portion, a sidewall insulating film disposed on the second region of the trench sidewall, a third region disposed on the second region of the trench bottom portion and having the same conductivity as and the higher impurity concentration than the second region, a fourth region disposed on the back surface of the semiconductor layer, a first electrode formed on each first region, a second electrode connected to the third region, and a third electrode formed on the fourth region.

High-breakdown-voltage semiconductor device

A high-breakdown-voltage semiconductor device includes a high-resistance semiconductor layer, first trenches formed on the surface thereof in a longitudinal plane shape and in parallel, a Schottky electrode formed thereon and sandwiched between adjacent first trenches, a first region having an opposite conductivity type to the semiconductor layer continuously disposed in a sidewall and a bottom of each of the first trenches, a sidewall insulating film disposed on the sidewall, a second region of the opposite conductivity type disposed in the bottom of each of the first trenches, a third region disposed on the opposite surface of the semiconductor layer, a control electrode filling each of the first trenches in contact with the second region and connected to the Schottky electrode, a backside electrode formed on the third region, wherein second trenches communicate with the first trenches at both ends of longitudinal sides thereof, and the Schottky electrode is surrounded by the first and second trenches.

A high withstand voltage semiconductor device does not show any significant fall of its withstand voltage if the impurity concentration of the RESURF layer of a low impurity concentration semiconductor region thereof varies from the optimal level and/or influenced by the fixed electric charge. The device is produced by forming a ring-shaped high impurity concentration edge termination layer of a second conductivity type and a ring-shaped low impurity concentration RESURF layer of the second conductivity type on the front surface of a semiconductor layer of a first conductivity type carrying electrodes respectively on the opposite surfaces thereof along the outer edge of one of the electrodes, then forming an outer ring layer with an impurity concentration substantially as low as the RESURF layer concentrically outside the RESURF layer with a gap separating therebetween and subsequently forming an inner ring layer with an impurity concentration substantially as high as the edge termination layer concentrically inside the RESURF layer.

High withstand voltage semiconductor device

A high withstand voltage semicnductor device does not show any significant fall of its withstand voltage if the impurity concentration of the RESURF layer of a low impurity concentration semiconductor region thereof varies from the optimal level and/or influenced by the fixed electric charge. The device is produced by forming a ring-shaped high impurity concentration edge termination layer of a second conductivity type and a ring-shaped low impurity concentration RESURF layer of the second conductivity type on the front surface of a semiconductor layer of a first conductivity type carrying electrodes respectively on the opposite surfaces thereof along the outer edge of one of the electrodes, then forming an outer ring layer with an impurity concentration substantially as low as the RESURF layer concentrically outside the RESURF layer with a gap separating therebetween and subsequently forming an inner ring layer with an impurity concentration substantially as high as the edge termination layer concentrically inside the RESURF layer.

A set associative cache system in a computer system having a lower memory is provided with a plurality of cache memory sets. A cache data memory contains a plurality of cache lines to store data in units of blocks corresponding to data stored in the lower memory. A cache tag memory stores lower memory addresses for data stored in the cache lines. The plurality of cache memory sets have different numbers of cache lines. A read/write section reads out data stored in the lower memory into the plurality of cache lines and writing data in the plurality of cache lines back to the lower memory.

Growing community of inventors

Yokohama, Japan

Tetsuo Hatakeyama