Sony Corporation

Sony Semiconductor Solutions Corporation

Tetsuo Gocho

Junichi Sato

Tohru Ogawa

Shinichi Miyake

Kazuyuki Tomida

Yuzo Fukuzaki

Hideaki Hayakawa

Masanori Tsukamoto

Masami Nagata

Yasushi Morita

Tetsuji Nagayama

A semiconductor device includes a base, a first FET that includes at least two channel structure portions laminated, the channel structure portions each including a channel portion having a nanowire structure, a gate insulation film, and a gate electrode, and a second FET that includes a channel forming layer, a gate insulation layer, and a gate electrode. The first FET and the second FET are provided above the base. The channel portions of the first FET are disposed apart from each other in a laminating direction of the channel structure portions. Assuming that each of a distance between the channel portions of the first FET is a distance L1 and that a thickness of the gate insulation layer of the second FET is a thickness T2, T2≥(L1/2) is satisfied.

Semiconductor device including a field effect transistor with nanostructure based laminated channel structure and a field effect transistor with a single channel structure

A solid-state image sensor according to the present disclosure includes a first semiconductor substrate having a photoelectric conversion element and a second semiconductor substrate facing the first semiconductor substrate with an insulating film interposed therebetween, in which the second semiconductor substrate has an amplification transistor that amplifies an electrical signal output from the photoelectric conversion element on a first main surface (MSa), has a region having a resistance lower than a resistance of the second semiconductor substrate on a second main surface (MSb) opposite to the first main surface (MSa), and is grounded via the region.

Solid-state image sensor

Semiconductor device

A semiconductor device includes a base, a first FET that includes at least two laminated channel structure portions, the channel structure portions each including a channel portion having a nanowire structure, a gate insulation film, and a gate electrode, and a second FET that includes a channel forming layer, a gate insulation layer, and a gate electrode. The first FET and the second FET are provided above the base. The channel portions of the first FET are disposed apart from each other in a laminating direction of the channel structure portions. Assuming that each of a distance between the channel portions of the first FET is a distance Land that a thickness of the gate insulation layer of the second FET is a thickness T, T&#x2265;(L/2) is satisfied.

A semiconductor device according to an embodiment of the present disclosure includes: an SOI substrate in which a silicon substrate layer, a first insulating layer, and a semiconductor layer are layered in this order; a first transistor provided on the semiconductor layer; a second transistor provided on the silicon substrate layer and withstanding a higher voltage than the first transistor; and an element separation film provided between the first transistor and the second transistor, in which the element separation film includes a second insulating layer embedded in an opening that penetrates the semiconductor layer and the first insulating layer and reaches an inside of the silicon substrate layer, and a portion of the second insulating layer constitutes a gate insulating film of the second transistor.

Semiconductor device, method of manufacturing semiconductor device, and electronic apparatus

Method of manufacturing a semiconductor device

In a method of fabricating electronic components of the type wherein trenches formed in a substrate are filled up with a filling material deposited by a deposition process achieving etching and deposition concurrently, the improvement which comprises portions of the filling material deposited on those portion of the substrate other than those corresponding to the trenches are leveled up to the same height by an additional deposition of the filling material, or alternatively by a full-surface etch back process. With this leveling of the deposited material, a subsequent polishing operation can be performed smoothly with high accuracy. During the polishing operation, the resistance between a conductive polish-stop layer on the substrate and a surface of a polishing member contacting the substrate is monitored to determine a polish end.

Method of fabricating electronic devices of the type including smoothing process using polishing

A method of forming a multi-layer interconnection in which through-holes are formed in an interlayer insulating layer positioned between two neighboring mid interconnection layers, which through-hole is used for establishing an electrical interconnection between upper and lower interconnection layers, comprising the steps of forming an offset insulating film on said mid interconnection layer such that the patterns of the mid interconnection layer and the offset insulating film are the same; forming a sidewall insulating film on the lateral wall surface of a pattern made up of said mid interconnection layer and the offset insulating film; substantially conformally forming an etch stop layer covering the entire surface of the substrate, said etching stop layer being slower in etch rate than said interlayer insulating film; anisotropically etching said interlayer insulating film in a region having an opening size smaller than the spacing between the interconnecting layers; selectively removing the etching stop layer exposed on the bottom surface of said region for completing the through-hole; and filling said through-hole with an electrically conductive material.

Method for forming multi-layer interconnections

A method of determining an optimum condition of an anti-reflective layer upon forming a resist pattern by exposure with a monochromatic light, forms the anti-reflective layer with these conditions and forms a resist pattern using a novel anti-reflective layer. The method comprises (I) forming an equi-contour line for the amount of absorbed light regarding a photoresist of an optional film thickness using the optical condition of the anti-reflective layer as a parameter, (II) conducting the same procedure as in (I) above for a plurality of resist film thicknesses, (III) finding a common region for the amount of absorbed light with respect to each of the traces obtained, thereby determining the optical condition for the anti-reflective layer, (IV) applying same procedures as described above while changing the condition of the anti-reflective layer, thereby determining the optical condition for the anti-reflective layer, and (V) determining the optimum optical condition such as the kind and the thickness of the anti-reflective layer under a certain condition of the anti-reflective layer.

Semiconductor device containing Si, O and N anti-reflective layer

Method of forming a photoresist pattern using an anti-reflective

Anti-reflective layer used to form a semiconductor device

A multilayer resist pattern forming method patterns a lower resist layer formed over the stepped surface of a workpiece by a high-speed, highly anisotropic ion mode etching using an intermediate pattern formed by etching an intermediate layer formed by a high-density plasma CVD process as a substantial etching mask. The intermediate layer formed by the high-density plasma CVD process has a dense film quality and highly resistant to ion bombardment. Therefore, the intermediate resist pattern is neither thinned nor contracted and, consequently, the lower resist pattern can be formed precisely in conformity with the design rule. Since the high-density plasma promotes interaction between source gases to enable the intermediate layer to be formed at a comparatively low processing temperature, which prevents damaging the lower resist layer by heat.

Multilayer resist pattern forming method

A semiconductor device in which patterning is effected using a silicon oxynitride (SiON) based thin film as an anti-reflection film and in which electrical properties are prohibited from being deteriorated by hydrogen contained in the SiON based thin film. The semiconductor device has a substrate, a gate insulating film formed on the surface of the substrate, a gate electrode formed on the gate insulating film, and a first antireflection film having a pattern in common with the gate electrode. The semiconductor device also has a hydrogen permeation prohibiting film formed between the gate insulating film and the first antireflection film. The first antireflection film contains hydrogen and is formed on the gate electrode.

Semiconductor device with antireflection film

A method of forming a metal plug, including a step of flattening by polishing the surface of a contact plug which is formed by etching back a metal layer, for example, a deposited layer of Blk-W on a substrate. It also makes it possible to print a wiring metal layer by a lithographic process which has thus far been considered difficult to apply to Blk-W. In the method of the invention, a contact hole 3 is opened in an insulation film layer 2 on a substrate 1, and, after coating an adhesion layer 4, a metal layer 5 is deposited on the entire surface. Thereafter, the surface of the metal layer 5 is flattened by a polishing operation, and etched back to form a metal plug 7.

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Kanagawa, Japan

Tetsuo Gocho