Megachips Corporation

Tetsuo Furuichi

Takahiko Sugahara

Takashi Oshikiri

Ikuo Yamaguchi

Shinji Tanaka

Tetsuji Kajitani

Masayuki Imagawa

Takahiro Masuda

Fumiaki Tsukazaki

Masakazu Nishimoto

Yasuhisa Marumo

Takeyoshi Hashimoto

A technique for improving data security is provided. To be specific, in a memory system including an information processing apparatus and a semiconductor memory device, the semiconductor memory device has an interface section that transmits, to the information processing apparatus, data read out from a memory core according to a plurality of communication protocols having different signal transmission/reception methods. Based on a switch command inputted from the information processing apparatus, a communication protocol selection section inputs, to the interface section, a selection signal for selecting a particular communication protocol from the plurality of communication protocols.

Memory control device, semiconductor memory device, memory system, and memory control method

A technique allowing an improvement in the confidentiality of information stored in a memory device. A memory controller includes a key generation part that newly generates key information for use in encryption and decryption of information at every predetermined timing, and a data conversion circuit that encrypts information to be outputted to a memory device based on the information and decrypts encrypted information inputted from the memory device based on the key information. In the data conversion circuit, each time the key generation part generates new key information, key information is updated so as to set the new key information as the key information.

Memory controller, memory control apparatus, memory device, memory information protection system, control method for memory control apparatus, and control method for memory device

An address comparator stores an address of data read out by a host system. Also, a buffer reads out the data from a memory and stores the data. If an address of data which is expected to be newly read out by the host system is included in addresses which have already been stored in the address comparator, the host systemnewly reads out the data from the buffer, not from the memory. As a result, it is possible to eliminate or lessen the possibility of unintentional rewriting of data which is likely to be caused due to repeated readout of data.

Memory controller for suppressing read disturb when data is repeatedly read out

A memory controller carries out error detection on a wide range of area of a memory cell array, which includes not only readout addresses but also non-readout addresses. Thus, by carrying out error detection at an address at which an error occurs without accessing the address for readout, it is possible to detect occurrence of an error at the address. Accordingly, it is possible to prevent a 'read disturb phenomenon' in which repetition of access to a readout address for readout may probably cause an error at a non-readout address other than the readout address.

Memory controller

When a memory card is inserted into a computer, a memory controller sends command information stored in a memory array to the computer. Then, the computer stores the command information received from the memory card into a RAM. The computer generates a command as needed on the basis of the stored command information and sends the generated command to the memory card. When the memory card receives the command from the computer, the memory controller analyzes the received command and performs it while making reference to command analysis information. This makes it possible to reduce a load accompanying the change and addition of commands in a semiconductor memory.

Memory system and computer system

Whether the comparison value of temporarily stored data which is read out from a flash memory by a host system exceeds a threshold value related to a bit error or not is checked, and if the comparison value exceeds the threshold value, the temporarily stored data which is read out is rewritten into the flash memory. If the temporarily stored data has an error, the error is corrected by an error correction part and then the data is rewritten. The threshold value includes, e.g., the number of readouts, the number of bit errors and the number of accumulated occurrences of bit errors. The present invention is suitable for prevention of bit errors due to read disturb and can recover the bit data which changes with time, and therefore makes it possible to improve the reliability of the flash memory by preventing occurrence of bit errors.

Bit error prevention method and information processing apparatus

A memory control method includes writing converted data which is produced by carrying out a code conversion on original data into a memory. An amount of 1s in the converted data is less than an amount of 1s in the original data. Further, the memory control method includes outputting reproduced data which is provided by carrying out an inverse transformation of the code conversion on the converted data which is read out from the memory, to a host system for processing the original data.

Memory control method and memory system

A memory controller for controlling data access to a memory comprises a refresh controller. A read count memory part included in the refresh controller counts the number of read operations on each page of the memory and stores the read count therein. If the read count for any page exceeds a predetermined number, the refresh controller rewrites data stored in this page into the memory.

A game cassette unit which can be connected to a game machine having a CPU for execution of a game selected by a user, including a memory which rewritably stores a plurality of game machine programs and a game selection program that allows a user to select a desired one of these programs. The memory further rewritably stores decode data defining address conversion rules for executing respective of the programs. A decode part executes address conversion based on decode data corresponding to the game selection program after start of power. After the user selects one of the game machine programs, the decode part executes address conversion based on the decode data corresponding to a selected game machine program. Thus, the user can select a desired one from the plurality of game machine programs. As a result, game software is provided to the user at low cost.

Game cassette unit with decode controller

According to an apparatus for automatically generating a logic circuit, when a request specification represented by a state transition diagram is input to the apparatus, the apparatus divides the specification into an information control part and an information processing part, divides the information control part into a transition state generator and a control signal generator, and specifies the transition state generator, the control signal generator, and the information processing part, as combinations of circuits, which are realized by combinations of logic elements and wirings, and wirings connecting the circuits. Therefore, the apparatus can easily cope with a change of use of the logic circuit, a change of a library of a final product, and the like. In addition, when only the state transition diagram, which represents request functions of the logic circuit naturally and compactly and which is easily described by an operator, is input to the apparatus, a large scale logic circuit can be automatically generated, thereby significantly reducing a time for developing the circuit.

Apparatus for automatically generating logic circuit

A simulation program conversion method and system is provided. The original simulation program is written by a function description language, such as Verilog-HDL, using a text editor, and, then, the original simulation program is converted into an executable program using a programming language, such as the C language, so that the simulation program may be compiled before execution. The speed of execution of the simulation program is significantly improved.

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Osaka, Japan

Tetsuo Furuichi