Hitachi, Ltd.

Renesas Electronics Corporation

Renesas Technology Corp.

Tetsuo Fujiwara

Takaaki Suzuki

Toshihide Nabatame

Kazutoshi Higashiyama

Hiroshi Nakano

Haruo Akahoshi

Takahiko Kato

Itaru Kanno

Yoshimi Sudo

Tomoryo Shono

Yukinori Hirose

Yuuji Takada

Yutaka Fukui

Masateru Suwa

Mitsuo Hayashibara

Masaru Kadoshima

Hideki Tamaki

Seiji Watahiki

Yasuhiko Murata

A semiconductor device having Cu wiring including a basic crystal structure which can reduce surface voids, and an inspecting technique for the semiconductor device. In the semiconductor device, surface voids can be reduced down to 1/10 or less of a current practical level by specifying a barrier layer and a seed layer and setting a proportion (frequency) of occupation of a coincidence site lattice (CSL) boundary having a grain boundary Sigma value 27 or less to all crystal grain boundaries of a Cu wiring to 60% or higher. Alternatively, a similar effect of surface void reduction can be obtained by specifying a barrier layer and a seed layer and setting a proportion (frequency) of occupation of a coincidence site lattice (CSL) boundary having a grain boundary Sigma value 3 to all crystal grain boundaries of a Cu wiring to 40% or higher.

Semiconductor device, manufacturing method of semiconductor device, semiconductor manufacturing and inspecting apparatus, and inspecting apparatus

A semiconductor device containing a dielectric capacitor having an excellent step coverage for a device structure of high aspect ratio corresponding to high integration degree, as well as a manufacturing method therefor are provided. A dielectric capacitor of high integration degree is manufactured by forming a bottom electrodeand a top-electrodecomprising a homogeneous thin Ru film with 100% step coverage while putting a dielectrictherebetween on substrateshaving a three-dimensional structure with an aspect ratio of 3 or more by a MOCVD process using a cyclopentadienyl complex within a temperature range from 180&#xb0; C. or higher to 250&#xb0; C. or lower.

Method of forming capacitor with ruthenium top and bottom electrodes by MOCVD

A ferroelectric capacitor of the type having a top electrode, a ferroelectric thin film, and a bottom electrode, is characterized in that said ferroelectric thin film is a perovskite-type oxide containing Pb and said upper and bottom electrodes contain an intermetallic compound composed of Pt and Pb. An electronic device is provided with said ferroelectric capacitor. This construction is designed to solve the following problems. In a non-volatile ferroelectric memory (FeRAM), a degraded layer occurs near the interface between the PZT and the electrode due to hydrogen evolved during processing or due to diffusion of Pb from the PZT into the electrode. A stress due to a difference in lattice constant occurs in the interface between the electrode and the ferroelectric thin film. The degraded layer and the interfacial stress deteriorate the initial polarizing characteristics of the ferroelectric capacitor and also greatly deteriorate the polarizing characteristics after switching cycles.

Ferroelectric capacitor and semiconductor device

A semiconductor device containing a dielectric capacitor having an excellent step coverage for a device structure of high aspect ratio corresponding to high integration degree, as well as a manufacturing method therefor are provided. A dielectric capacitor of high integration degree is manufactured by forming a bottom electrode and a top-electrode comprising a homogeneous thin Ru film with 100% step coverage while putting a dielectric therebetween on substrates having a three-dimensional structure with an aspect ratio of 3 or more by a MOCVD process using a cyclopentadienyl complex within a temperature range from 180&deg; C. or higher to 250&deg; C. or lower.

Semiconductor device and method for manufacturing the same

In a semiconductor device and production method thereof, a technique is used to prevent film separation of the bottom electrode occurring during a heat treatment process which is carried out to make the bottom electrode closely packed and in the heat treatment process for producing dielectric crystallization. In the production method, a glue layer including an insulator is formed between SiO insulation layer and the inner wall of a concave hole. The SiO layer is located on the Si board , and Si plug and a barrier layer are formed therein. A glue layer is formed on the inner wall of the hole of the SiO insulation layer , and a bottom electrode comprising Ru is formed on the barrier layer and glue layer . Dielectric film comprising BST and a top electrode comprising Ru are laminated sequentially on the bottom electrode , to form a dielectric device with the bottom electrode

Semiconductor device and production method thereof

A power generation gas turbine includes first stage turbine blades made of an alloy whose 10.sup.5 -hour 14-kgf/mm.sup.2 temperature capacity is 920.degree. C. or over, second and subsequent stage turbine blades made of an alloy whose 10.sup.5 -hour 14-kgf/mm.sup.2 temperature capacity is 800.degree. C. or over, first stage turbine nozzles made of an alloy whose 10.sup.5 -hour 6 kgf/mm.sup.2 temperature capacity is 900.degree. C. or over, and second and subsequent stage turbine nozzles made of an alloy whose 10.sup.5 -hour 6-kgf/mm.sup.2 temperature capacity is 800.degree. C. or over.

High efficiency gas turbine

Growing community of inventors

Hitachinaka, Japan

Tetsuo Fujiwara