Tohoku University

Kabushiki Kaisha Toshiba

Tokyo Electron Limited

Skhynix Inc.

Globalwafers Japan Co., Ltd.

Sharp Semiconductor Innovation Corporation

Nec Corporation

Tanaka Kikinzoku Kogyo K.k.

Toshiba Microelectronics Corporation

Power Spin Inc.

Tetsuo Endoh

Hideo Ohno

Shoji Ikeda

Hideo Sato

Riichiro Shirota

Hiroaki Honjo

Tomoharu Tanaka

Takahiro Hanyu

Shunsuke Fukami

Seiichi Aritome

Yoshiyuki Tanaka

Daisuke Suzuki

Ryouhei Kirisawa

Fujio Masuoka

Yoshiaki Saito

Hiroki Koike

Masaaki Niwa

Toru Tanzawa

Susumu Shuto

Kazunori Ohuchi

Gertjan Hemink

Masanori Natsui

Yitao Ma

Takashi Ohsawa

Kenchi Ito

Masaki Momodomi

Fumihiro Matsukura

Ryozo Nakayama

Kyota Watanabe

Koichi Nishioka

Hiroshi Iwahashi

Masamichi Asano

Satoshi Inoue

Akira Tamakoshi

Etsuo Fukuda

Sadahiko Miura

Seo Moon-Sik

Toshio Nakanishi

Shigeyoshi Watanabe

Minoru Honda

Shinya Ishikawa

Masayuki Kohno

Koji Izunome

Takashi Ishikawa

Shohei Matsumoto

Masakazu Muraguchi

Akira Mochizuki

Hui Shen

Mathias Bersweiler

Koji Sakui

Yoshihisa Iwata

Takashi Mori

Tadahiko Sugibayashi

Eiichi Nishimura

Yasuo Itoh

Yuji Kawaguchi

Noboru Sakimura

Keiichi Sasaki

Ryusuke Nebashi

Yukihide Tsuji

Hideko Odaira

Yoshihiro Hirota

Ayuka Tada

Tatsuo Nishita

Moon Sik Seo

Kunihiro Tanaka

Takao Asada

Haruo Sudo

Makoto Hatakeyama

Tatsuhiko Aoki

Shuichi Kubota

Daisuke Asakura

Soshi Sato

Hiroaki Cho

William Andrew Borders

Takashi Saito

Chaoliang Zhang

Ayato Ohkawara

Satoru Tanoi

Syuichiro Otao

Shuji Katoh

Yoshikazu Takahashi

Yoshihisa Sekiguchi

Aleksandr Kurenkov

Kunihiro Tsubomi

Yoshihisa Horikawa

Shigeo Ohyama

Kazuki Itoh

Hisashi Matsumura

Toshimasa Namekawa

Satoru Araki

Hiroshi Yoshida

Kazutaka Kamijo

Moriya Miyashita

Toru Iwabuchi

Yoshihiro Maruyama

Chaoling Zhang

Tetsuro Anekawa

Kosuke Kimura

Moon-Sik Seo

A computation processing device includes: a memory unit that retains computation data for weighting computation, and at least a part of which is a non-volatile storage region; a computation circuit unit that performs computation processing including the weighting computation by using a part or all of the computation data input from the memory unit; and a power gate unit that blocks power supply to a part or all of memory cells other than memory cells storing a part or all of the computation data input to the computation circuit unit in the computation processing when performing the computation processing, in the non-volatile storage region.

Computation processing device

A storage circuit includes a memory cell array of memory cells each including a variable resistance type element, a resistance-voltage conversion circuit RTto convert a resistance value of a memory cell MCto be read to a data voltage, a reference circuit and RTto generate a reference voltage, a sense amplifier to determine read data by receiving the data voltage and the reference voltage via first and second input terminals, respectively, and comparing both voltages with each other, and an analog buffer circuit arranged between the resistance-voltage conversion circuit RTand a first input terminal of the sense amplifier or between the reference circuit and RTand a second input terminal of the sense amplifier. Current driving capability of the analog buffer circuit is large.

Storage circuit provided with variable resistance type elements

Provided are a magnetic film, a magnetoresistance effect element and a magnetic memory which take advantages of atop-pinned structure and a bottom-pinned structure, maintain perpendicular magnetic anisotropy of magnetic layers in a fixing layer and allow strong pinning even in an annealing treatment after a protective film is formed. A fixing layer of a magnetic film has a basic configuration in which a first magnetic layer (), a first non-magnetic layer (), a first Pt layer (), a second magnetic layer () disposed adjacent to each other in this order. The magnetization directions of the first magnetic layer () and the second magnetic layer () are both a direction perpendicular to the film surface, and an antiferromagnetic coupling is formed between the first magnetic layer () and the second magnetic layer ().

Magnetic film, magnetoresistance effect element and magnetic memory

A magnetoresistance effect element includes a first reference layer, a first junction layer, a first divided recording layer, a second junction layer, a second divided recording layer, and a third junction layer. The first divided recording layer has a configuration having a high magnetoresistance ratio (MR ratio), and the second divided recording layer (3) has a configuration having a high effective magnetic anisotropy energy density (Kt).

Magnetoresistance effect element, magnetic memory, and film formation method for said magnetoresistance effect element

A silicon wafer is a Czochralski wafer formed of silicon. The wafer includes a bulk layer having an oxygen concentration of 0.5×10/cmor more; and a surface layer extending from the surface of the wafer to 300 nm in depth, and having an oxygen concentration of 2×10/cmor more.

Silicon wafer and method for producing silicon wafer

The present invention relates to a platinum-based sputtering target containing platinum or a platinum alloy. The platinum-based sputtering target of the present invention is characterized by a material structure in a thickness-direction cross section thereof. Specifically, when a thickness-direction cross section is equally divided into n sections (n=5 to 20) along a thickness direction, a region including (n−2) sections excluding both end sections is set as a determination region, and when an average grain size in each of the sections is measured in the determination region, as well as an average grain size in the entire determination region is measured, the average grain size in the entire determination region is 150 μm or less, and a coefficient of variation calculated based on the average grain size in each of the sections of the determination region is 15% or less.

Platinum-based sputtering target, and method for producing the same

A magnetic multilayer film for a magnetic memory element includes an amorphous heavy metal layer having a multilayer structure in which a plurality of first layers containing Hf alternate repeatedly with a plurality of second layers containing a heavy metal excluding Hf; and a recording layer that includes a ferromagnetic layer and that is adjacent to the heavy metal layer, the ferromagnetic layer having a variable magnetization direction.

Magnetic laminated film, magnetic memory element, magnetic memory, and artificial intelligence system

A semiconductor memory device includes a memory cell array including a plurality of memory cells each including a resistance change type memory element configured to store a resistance state and a switch, a read determination circuit that compares a measurement signal from the memory cell selected in the memory cell array with a reference signal to determine a resistance state so as to read information from the resistance change type memory element, and a reference signal correction unit that corrects a level of the reference signal based on a selected position of the memory cell in the memory cell array.

Semiconductor memory device and control device for semiconductor memory device

The present invention provides an access controller, and a data transfer method. The access controller controls accesses to the MRAM by reading data in advance and backing up the data when data is to be read from the MRAM.

Device, sensor node, access controller, data transfer method, and processing method in microcontroller

A semiconductor circuit device includes a first clock gating circuit that outputs a first gated clock signal generated from a clock signal and a first enable signal, a non-volatile first flip-flop that operates in response to a clock pulse of the first gated clock signal, an acquisition circuit that acquires data inputted from the first flip-flop according to a second enable signal that enables or disables the acquisition of the data from the first flip-flop, and a power gating circuit that supplies electric power to the first flip-flop and receives the first and second enable signals as power source control signals. The power gating circuit includes a power switch, and supplies the electric power to the first flip-flop by turning ON the power switch when the power source control signals have logical values that enable the clock signal or the acquisition of the data in the acquisition circuit.

Semiconductor circuit and support device for logic circuit design

Provided are a magnetic tunnel junction dement suppressing diffusion and penetration of constituent elements between a hard mask film, and a magnetic tunnel junction film and a protection layer, and a method for manufacturing the magnetic tunnel junction element. The magnetic tunnel junction element has a configuration in which a non-magnetic insertion layer () including Ta or the like is inserted beneath a hard mask layer ().

Magnetic tunnel junction device, method for manufacturing magnetic tunnel junction device, and magnetic memory

A clustering device includes: an evaluation score calculation section configured to calculate an evaluation score or evaluation scores for evaluating a classification result; a batch process section configured to classify multiple element data into clusters with an optimum number of clusters, based on the evaluation scores respectively obtained for different number of clusters by assigning each of the multiple element data to one of the clusters; an update process section configured to assign newly added element data to a cluster that is closest to the newly added element data among the clusters into which the multiple element data are classified by the batch process section; and a determination section configured to determine validity of a classification result after assigning the newly added element data to the cluster, based on the evaluation score obtained by assigning the newly added element data to the cluster by the update process section.

Clustering device and clustering method

A method for producing a three-dimensional structure, a method for producing a vertical transistor, a vertical transistor wafer, and a vertical transistor substrate, capable of suppressing the emission of Si due to a heat treatment and making an interface between an oxide film and a core mainly consisting of Si relatively smooth include: forming a three-dimensional shape by processing (for example, by etching) a surface layer of a monocrystalline silicon substrate, the surface layer having an oxygen concentration of 1×10atoms/cmor more; and then forming an oxide film on the surface of the three-dimensional shape by performing a heat treatment. The three-dimensional structure has a shape having projections and recesses in a thickness direction of the silicon substrate, and a height in the thickness direction of the silicon substrate is between 1 nm and 1000 nm, and preferably between 1 nm and 100 nm.

Method for producing three-dimensional structure, method for producing vertical transistor, vertical transistor wafer, and vertical transistor substrate

The present invention provides a device with low power and high performance, which can be applied to sensor nodes, a sensor node using the same, an access controller, a data transfer method, and execute a processing method in a microcontroller. The device has: an MRAM; a non-volatile CPU configured to include a nonvolatile memory; a non-volatile FPGA-ACC configured to include a nonvolatile memory and execute a part of operations on the nonvolatile CPU; and a power-gating control unit that controls power supply to each memory cell in the MRAM, the non-volatile CPU, and the non-volatile FPGA-ACC. The device is further provided with an access controller that controls accesses to the MRAM by reading data in advance and backing up the data when data is to be read from the MRAM.

There is provided a neural network circuit device including a plurality of synapse circuits storing a synaptic coupling weight and a neuron circuit connected to the plurality of synapse circuits. The plurality of synapse circuits store the synaptic coupling weight in a non-volatile manner and output a voltage signal having a magnitude based on the stored synaptic coupling weight in response to an input signal. The neuron circuit includes a neuron MOS transistor having a floating gate and a plurality of control gates which are capacitively coupled to the floating gate and to which the voltage signals from the plurality of synapse circuits are input respectively, and a pulse generator outputting a pulse signal by turning on or off the neuron MOS transistor.

Neural network circuit device

Growing community of inventors

Sendai, Japan

Tetsuo Endoh