Fujitsu Corporation

Fujitsu Semiconductor Limited

Tetsuo Ashizawa

Wataru Yokozeki

Hideo Akiyoshi

Hideyuki Amada

An SRAM macro operates in a normal operation mode in which a plurality of memory-cell array blocks are accessible and in a low power mode in which bit lines in the memory-cell array blocks are left floating. When the SRAM macro returns from the low power mode to the normal operation mode, the bit lines in only memory-cell array blocks to be accessed among the plurality of memory-cell array blocks are precharged in sequence. This allows the peak of precharging current flowing into the SRAM macro to be dispersed.

Semiconductor storage having different operation modes

2data transfer signal lines are provided between transmitting and receiving sides of data on n signal lines in order to reduce power consumption required for a data transfer even if the number of bits of data to be transferred increases. The transmitting side has an encoder for outputting a signal of a low potential to one signal line and a signal of a high potential to the other signal lines among the 2data transfer signal lines in response to an input of transfer data from the n signal lines. The receiving side has a decoder for outputting the similar data as the transfer data to n signal lines in response to inputs from the 2data transfer signal lines.

Data transfer system

Each of memory blocks includes word line groups each having at least one of word lines, memory cells and bit lines. A decoder unit selects couple control units corresponding to the memory blocks to be accessed, and decodes an address signal to select any of the word line groups. A logic of the decoder unit is formed by assigning a bit of the address signal to identify the memory blocks and the couple control units lower than a bit of the address signal to identify the word line groups. Accordingly, the numbers of word lines disposed at the memory blocks can be equalized with each other, and lengths of the bit lines can be shortened. As a result, a wiring delay of each of the bit lines can be minimized, and an access time of a compiled memory can be shortened.

Compiled memory, ASIC chip, and layout method for compiled memory

An electric fuse is formed over a semiconductor substrate, the electric fuse being broken when a current flows therethrough. A breaker transistor is formed in a first surface layer of the semiconductor substrate of a first conductivity type, the breaker transistor including a source region, a drain region and a gate electrode. The source and drain regions sandwiches a channel region. The gate electrode controls a conduction state between the source and drain regions. The drain region is connected to one end of the electric fuse. A breaker pad is connected to the end of the electric fuse to supply a fusing current to the electric fuse. A back-bias pad applies a fixed voltage to the first surface layer independently from both a power supply voltage and a ground potential. A fuse information read circuit reads a breakdown/non-breakdown state of the electric fuse.

Semiconductor device with electrically broken fuse and its manufacture method

A plurality of p-MOSFETs connected to a power supply line is turned on to precharge bit lines. A precharge cancel signal generated by a NOR circuit and an inverter performs precharge control to turn off the p-MOSFETs to set the bit lines in a floating state during the period of a standby mode, or turn on the p-MOSFETs to precharge the bit lines during the period of a read mode or write mode.

Static semiconductor memory device and method of controlling the same

A shift register is sequentially supplied via a clock pad and a data pad with a clock and data indicating whether or not an electric fuse circuit is cut off. The supply turns on a switch corresponding to an electric fuse circuit to cut off, and connects the electric fuse circuits to cut off to a voltage supply line. Here, by supplying a high voltage to the voltage supply line via a voltage pad, electric current flows through electric fuse circuits to cut off in each chip area, thereby cutting off the electric fuse circuits at the same time. Providing the clock pad, data pad, voltage pad common to the electric fuse circuits in each chip area makes it possible to reduce the size of a scribe area. This allows increase in the number of semiconductor chips producible per semiconductor wafer, resulting in reduced manufacturing cost thereof.

Semiconductor integrated circuit

A word line control circuit controls a high-level voltage value representing that a plurality of word lines are unselected in each of an access mode and non-access mode on the basis of a control signal for controlling the high-level voltage value of the word lines and a control signal output from a main decoder.

First buffers of a first driver circuit generate voltages to be supplied to word lines, respectively. Second buffers of a second driver circuit operate in synchronization with the first buffers to generate voltages to be supplied to first substrate lines, respectively. Each second buffer, upon access to memory cells, supplies a voltage for lowering the threshold values of transfer transistors and driver transistors to its corresponding first substrate line, and supplies thereto a voltage for raising the threshold values of the transfer transistors and the driver transistors during standby. This can improve the operation speed at the time of accessing the memory cells and reduce the leak current during standby. This results in shortening the access time during the operation of the semiconductor memory and reducing the standby current during standby.

Semiconductor memory

A semiconductor memory device comprises a memory cell array, a decoder unit selecting a word line of the memory cell array, a first dummy cell array connected to a first dummy bit line and disposed with the memory cell array at a first location away from the decoder unit along the word line, a second dummy cell array connected to second dummy bit lines and disposed with the memory cell array at a second location away from the decoder unit along the word line, the second location being farther from the decoder unit than the first location, and a timing control unit determining timing of activation and deactivation of an internal control signal.

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Kawasaki, Japan

Tetsuo Ashizawa