Kabushiki Kaisha Toshiba

Mitsubishi Electric Corporation

Mitsubishi Denki Kabushiki Kaisha

Tetsujiro Tsunoda

Masaru Ando

Nobuhiro Shingai

Yoshikatsu Nagashima

Kazunari Nishitani

Takuya Hamaguchi

Toru Takeda

Mitsuhiko Kitagawa

Akihiko Osawa

Makoto Hideshima

Satoshi Nakao

Hideki Haruguchi

Shigeo Tooi

Shinichi Umekawa

Toru Ichimura

Shingo Yanagida

Masanori Yamamoto

Yoshiro Baba

Hiroshi Fujita

Tadashi Matsuda

Eisuke Suekawa

Masakatsu Takashita

Takahiro Ito

Shinjiro Kojima

Kaoru Imamura

Hidetoshi Nakanishi

Yasuo Ata

Masashi Kuwahara

Kazunobu Nishitani

Shunsuke Sakamoto

Takahiro Okuno

Jun Onodera

Hiroki Muraoka

Toshinari Hirai

Hidekazu Sugawara

Shoko Kanazawa

An object is to provide a technique capable of suppressing the rise in the sense voltage during the Miller plateau. A semiconductor device includes a semiconductor substrate of first conductivity type, a first IGBT portion and a second IGBT portion selectively disposed on a first main surface of the semiconductor substrate, and an impurity region of second conductivity type selectively disposed on a second main surface of the semiconductor substrate. The second IGBT portion is used to detect the current passing through the first IGBT portion. An area ratio of the impurity region within a second range to an area of the second range is lower than an area ratio of the impurity region within a first range to an area of the first range, the second range corresponding to the second IGBT portion, the first range corresponding to the first IGBT portion.

Semiconductor device

It is an object to provide a technique where a snubber capacitor having an appropriate capacitance is usable. A power module includes: a third lead having one end electrically connected to a first connection point and the other end exposed from a package, where the third lead is shorter than a first lead; and a fourth lead having one end electrically connected to a second connection point and the other end exposed from the package, where the fourth lead is shorter than a second lead. A snubber capacitor is attachable to and detachable from the other ends of the third lead and fourth lead.

Power module

According to the present invention, a semiconductor device includes a first metal plate, a second metal plate provided above the first metal plate, a third metal plate provided above the second metal plate, a first semiconductor chip provided between the first metal plate and the second metal plate, a second semiconductor chip provided between the second metal plate and the third metal plate and a cooling member, wherein the first metal plate has a first cooling portion that is in contact with the cooling member, the second metal plate has a second cooling portion that is in contact with the cooling member, and the third metal plate has a third cooling portion that is in contact with the cooling member.

Provided is a power module having a sufficient space in which a large electronic component in size is disposed, and having yield strength against external stresses, such as vibrations. A power module includes: an insulating substrate; a semiconductor element mounted above the insulating substrate; a sealant sealing the insulating substrate and semiconductor element, and forming the outer shape of the power module; and a pair of terminals disposed on the sealant, in both ends of the sealant in a width direction of the power module in an upright manner. The pair of terminals are spaced from each other by a distance greater than the width of a film capacitor being a first electronic component mounted on the bottom surface of a control substrate being a circuit substrate coupled to tips of the pair of terminals. The pair of terminals are longer in a height direction than the film capacitor.

A semiconductor chip testing method includes: (a) testing the electrical characteristics of each of semiconductor chips in the form of wafers or in the form of chips formed on a predetermined number of semiconductor wafers having certain relationship, and determining if the semiconductor chip is non-defective or defective; (b) calculating a percentage of semiconductor chips determined to be defective as a fraction defective for each of wafer addresses based on determination results about the semiconductor chips on the predetermined number of semiconductor wafers, the wafer addresses indicating the respective positions of the semiconductor chips on the semiconductor wafers; and (c) changing a determination result about a semiconductor chip determined to be non-defective to defective, the semiconductor chip being at a wafer address determined to have a fraction defective at a threshold or higher than the threshold.

Semiconductor chip testing method and semiconductor chip testing device

A semiconductor device includes a semiconductor substrate, a surface electrode formed on the semiconductor substrate, an ineffective region formed to surround the surface electrode, and an ID-indicating portion made of a different material than the surface electrode and formed on the surface electrode to indicate an ID. The area of the ineffective region is smaller than the area of the surface electrode.

An IGBT comprises trenches arranged in strips, first emitter diffusion layers formed so as to extend in a direction intersecting the trenches, and contact regions formed to have a rectangular shape. The portions of the contact regions on the first emitter diffusion layers have a smaller width than the other portions, the width extending in the direction intersecting the trenches. This configuration allows for an increase in the emitter ballast resistance of the emitter diffusion layers, resulting in enhanced resistance to electrical breakdown due to short circuit.

Insulated gate bipolar transistor having contact region with variable width

The present invention is a power device includes, a first conductive type semiconductor substrate, a second conductive type base region formed on a surface of the semiconductor substrate, a second conductive type collector region formed on a rear surface of the semiconductor substrate, a first conductive type emitter region formed on a surface of the base region, a trench gate formed via a gate insulating film in a first trench groove formed in the base region so as to penetrate the emitter region, a dent formed in the base region in proximity to the emitter region, a second conductive type contact layer formed on an inner wall of the dent, having a higher dopant density than that of the base region, a dummy trench formed via a dummy trench insulating film in a second trench groove formed at a bottom of the dent, and an emitter electrode electrically connected to the emitter region, the contact layer and the dummy trench, wherein the trench gate and the dummy trench reach the semiconductor substrate.

Power device

One of the aspects of the present invention is to provide a semiconductor device, which includes a case, and an insulating substrate provided within the case. It also includes a plurality of semiconductor chips mounted on the insulating substrate, each of which has a first chip electrode for receiving a control signal, and a flexible board supported by the case, which includes a body portion and a plurality of lead portions extending from the body portion. Each of the first chip electrodes is electrically connected with the respective one of the lead portions.

Semiconductor device having a flexible board for connection to a semiconductor chip mounted on an insulating substrate

A method for manufacturing a semiconductor device according to the present invention has a step of forming a plurality of MOSFETs each having a channel of a first conductivity type in a stripe on the first major surface of a wafer; a step of implanting an impurity of a first conductivity type into the second major surface of the wafer, and performing a laser annealing treatment in a stripe leaving equidistant gaps, to form a buffer layer that has been activated in a stripe; a step of implanting an impurity of a second conductivity type into the second major surface of the substrate after forming the buffer layer, and performing a laser annealing treatment on the entire surface of the second major surface, to form a collector layer, and to activate the buffer layer; and a step of forming an emitter electrode on the first major surface, and forming a collector electrode on the second major surface.

Semiconductor device with enhanced switching speed and method for manufacturing the same

Second diffusion layers to be guard rings of a second conductivity type are formed on the major surface of a semiconductor substrate of a first conductivity type in a guard ring region. An insulating film is formed on these second diffusion layers. The semiconductor device has a structure wherein a conductive film is formed on the insulating film between adjacent electrodes among a first surface electrode, second surface electrodes, and a third surface electrode.

Semiconductor device having an improved structure for high withstand voltage

A method of manufacturing a low power dissipation semiconductor power device is provided which is easy to perform and suitable for mass production. When a first and second conductivity-type regions are formed on a semiconductor substrate which is selectively irradiated by impurity ions, an excellent super junction is formed by controlling the ion acceleration energy and the width of each irradiated region so that the first and second conductivity-type regions may have a uniform impurity distribution and a uniform width along the direction of irradiation. Another method of manufacturing a low power dissipation semiconductor power device having an excellent super junction is provided which selectively irradiates a collimated neutron beam onto a Psilicon ingot and forms an Nregion that has a uniform impurity distribution and a uniform width along the direction of irradiation in the Psilicon ingot.

Manufacturing method of semiconductor device

A charge storage layer of first conductive type is formed on the first principal surface of a semiconductor substrate. A base layer of second conductive type is formed on the charge storage layer. Each trench formed through the base layer and the charge storage layer is lined with an insulating film and filled with a trench gate electrode. Dummy trenches are formed on both sides of each trench. Source layers of first conductive type are selectively formed in the surface of the base layer and in contact with the sidewalls of the trenches. The source layers are spaced apart from each other and arranged in the longitudinal direction of the trenches. A contact layer of second conductive type is formed in the surface of the base layer and between each two adjacent source layers arranged in the longitudinal direction of the trenches. A collector layer of second conductive type is formed on the second principal surface of the semiconductor substrate.

Insulated gate transistor

A semiconductor device with high turn off capability includes a plurality of stripe trench lines which are provided in each of adjacent cell regions of a semiconductor layer in parallel and extended from one cell region toward the other cell region, a gate insulating film formed in each of the trench lines, and a gate electrode embedded in each of the trench lines with the gate insulating film interposed therebetween. In this semiconductor device, in each of the cell regions, part of adjacent ends of the plurality of trench lines on a side of the other cell region are connected to each other by connecting portions, and portions between the remaining adjacent ends are open. Moreover, at least one of the connecting portions of one cell region faces one of the open portions of the other cell region.

Growing community of inventors

Tokyo, Japan

Tetsujiro Tsunoda