Fujitsu Corporation

Tetsuji Takeguchi

Takao Akaogi

Yasushi Kasa

Yasushige Ogawa

Kiyoshi Itano

Hiromi Kawashima

Shouichi Kawamura

Ryoji Hagiwara

Yoshikazu Homma

Hiroshi Mawatari

Osamu Iioka

Haruo Shoji

A redundancy substitution method for memory cells within an electrically writable and erasable semiconductor memory device, includes detecting a memory cell having a tendency of a charge loss and/or a charge gain, by use of a charge loss detecting reference cell and/or a charge gain detecting reference cell. The charge loss detecting reference cell has a threshold value set between a threshold value of a read reference cell and a threshold value of a write verify reference cell that is higher than that of the read reference cell, and the charge gain detecting reference cell has a threshold value set between the threshold value of the read reference cell and a threshold value of an erase verify reference cell that is lower than that of the read reference cell. The method subjects a memory cell whose tendency of the charge loss and/or the charge gain is detected to a redundancy substitution.

Redundancy substitution method, semiconductor memory device and information processing apparatus

A nonvolatile semiconductor memory device includes a control circuit configured to perform a first block erase operation that erases nonvolatile memory cells together in a lump such that threshold voltages of the memory cells are set lower than a first erase verify voltage, to check whether a threshold voltage of each of the nonvolatile memory cells is lower than a first erase-degree-check voltage after the first block erase operation, to perform a first write-back operation in response to a check result indicating that the threshold voltage is lower than the first erase-degree-check voltage, thereby raising the threshold voltage above a voltage higher than the first erase-degree-check voltage, and to perform a second block erase operation that erases the nonvolatile memory cells together in a lump after the first write-back operation such that the threshold voltages of the memory cells are set lower than a second erase verify voltage.

Nonvolatile semiconductor memory device performing erase operation that creates narrow threshold distribution

The present invention provides a semiconductor memory device that performs a highly reliable data read operation at a high speed. This semiconductor memory device reads data stored in memory cells in accordance with a result of a comparison between a signal read out from the memory cells, which are connected to a word line, with a signal read out from a reference cell connected to a reference word line. This semiconductor memory device includes a load capacity adjustment circuit that adjusts the timing of starting up the gate of the reference cell in accordance with each location of the connection of the memory cells to the word line.

Semiconductor memory device having a resistance adjustment unit

Semiconductor device having a high-speed data read operation

Semiconductor memory device having high speed data read operation

A semiconductor memory device which can reduce a time required for a write-protection setting operation when a plurality of blocks are to be write-protected. A write area of the semiconductor memory device is divided into a predetermined number of blocks each of which is rewritable on an individual block basis. Write-protection information is simultaneously provided to a plurality of blocks that are arbitrarily designated from among the predetermined number of blocks so that the plurality of blocks are simultaneously subjected to the write-protection setting operation.

Semiconductor memory device for reducing a time needed for performing a protecting operation

A flash memory performs channel erasing or source erasing by applying a negative voltage to a control gate. The device includes a voltage restriction device which restricts the negative voltage to be applied to the control gate so that the negative voltage will be a constant value relative to the voltage of the channel or source. Alternatively, two voltage restricting devices restrict the negative voltage applied to the control gate and the voltage to be applied to the source so that the voltages will be a constant value relative to a common reference voltage.

Flash memory with improved erasability and its circuitry

A negative-voltage circuit for realizing a flash memory is installed independently and is applied selectively to word lines in response to signals sent from row decoders. Row decoders for specifying word lines need not be installed in the negative voltage circuit. The negative circuit can therefore be reduced in scale.

Negative voltage circuit for a flash memory

The present invention relates to improvements in erasing a flash memory. An object of the present invention is to shorten the erasing time. During pre-erase writing, at least either word lines or bit lines are selected in units of multiple lines at a time, and data are written in multiple selective transistors simultaneously.

Drive circuit for flash memory with improved erasability

An exclusive OR circuit includes a first series circuit in which a source of a first pMIS transistor is connected to a positive-voltage power supply line. A drain of the first pMIS transistor is connected to a drain of a first nMIS transistor via a second nMIS transistor. The source of the first nMIS transistor is connected to a low-voltage power supply line via a fourth nMIS transistor. A second series circuit has a drain of a third nMIS transistor connected to a high-voltage power supply line via a second pMIS transistor. The source of the third nMIS transistor is connected to the source of a third pMIS transistor. The drain of the third pMIS transistor is connected to the low-voltage power supply line via a fourth pMIS transistor. The gates of the first and third nMIS transistors and the first and third pMIS transistors are connected to one another and provided with a first input. The gates of the second and fourth nMIS transistors and the second and fourth pMIS transistors are connected to one another and provided with a second input. The sources of the second and third nMIS transistors are connected to each other and provide the exclusive OR of the first and second inputs.

XOR CMOS logic gate

The purpose of the present invention is to provide an electrically erasable nonvolatile semiconductor memory that permits correct data readout despite the occurrence of over-erased memory cells. In the nonvolatile semiconductor memory of the invention, a select transistor whose gate is connected to a word line is provided for each group consisting of a plurality of memory cells, and the sources of the memory cells in the same group are connected to a common source via the select transistor. For writing and erasure, the source-drain relationship is reversed from that previously practiced, so that for writing the drain is grounded and a positive voltage is applied to the source while for erasure the source is grounded and a high voltage is applied to the drain. In a nonvolatile semiconductor memory according to another mode of the invention, a source line is provided independently for every one or a plurality of word lines. For reading, the source line, word line, and bit line to which the memory cell selected for reading is connected are supplied with a lower supply voltage, a higher supply voltage, and a positive voltage lower than the higher supply voltage, respectively, while the source lines and word lines to which the selected memory cell is not connected are supplied with the higher supply voltage and the lower supply voltage, respectively, and the bit lines to which the selected memory cell is not connected are opened.

Electrically erasable nonvolatile semiconductor memory that permits data

In order to facilitate a test of the operations of a semiconductor memory device, the semiconductor memory device includes a line selection checking unit coupled to a cell matrix and column gates to form a logic gate circuit unit consisting of a plurality of transistors, the gates of the transistors being connected to word lines or bit lines. The line selection checking unit has a voltage or current detection portion connected to a pad for detecting an output voltage or current of the line selection checking unit.

Growing community of inventors

Kawasaki, Japan

Tetsuji Takeguchi