Hitachi, Ltd.

Tetsuji Ogawa

Takao Satoh

Toshiyuki Kinoshita

Tadashi Sato

Hitoshi Ueno

Hiroaki Odawara

Masao Kato

Masaichiro Yoshioka

Kazuhiko Ninomiya

Ryo Yamagatu

A channel processor (CHP) within a channel apparatus instructs parallel transfer of data through a plurality of channels within a channel cluster (CCL), when it reads out a LCUW. Each of the channels sequentially generates addresses of a main storage determined based on numbers of respective channels under control of a control section and a channel data controller (CDC) accesses the main storage according to the generated addresses to read out data. Those channels transfer the data in parallel to an auxiliary storage device through an optical fiber cable set. This auxiliary storage device includes a plurality of channel ports, two buffer control circuits, a buffer and a high speed storage unit. The buffer has a two-face structure, each of the faces having 2 kilo-bytes. One of the buffer control circuits receives data from the channel ports through the optical fiber cable set in the plurality of channels and selects either one of the faces of the buffer to write them therein. As soon as all the received data are written in either one of the faces of the buffer, they are read out by the other of the buffer control circuits to be written in the high speed storage unit.

Channel apparatus having a plurality of channels capable of being

In a highspeed and large-capacity data transfer operation effected between an extended storage unit and an input/output unit, such a data transfer system is provided, capable of preventing a performance deterioration caused by a lack of main storage capacity with employing a buffer having a large memory capacity, and deterioration of a transfer throughput caused by an overhead of an input/output operation due to a use of a buffer having a small memory capacity. There are provided a CCW for directly designating the extended storage unit as an object of a data transfer operation, and a signal line for initiating from a channel the data transfer operation between HSA-extended storage unit. Furthermore, buffers having the planes and with a small memory capacity are prepared on the HSA. The data transfer operation is carried out between the channel and the buffer with one plane, and the data transfer operation is performed between the extended storage unit and the buffer having the other plane in parallel with the first-mentioned data transfer operation. After the data transfer operations have been accomplished, a data transfer operation for the next block is executed by substituting one plane with the other plane.

Data transfer system

An input/output control system includes an external data controller connected to a plurality of input/output units, a central processor, and a main storage accessible from the external data controller and the central processor. The main storage has a storage area corresponding to each input/ouptut unit and a storage area storing information to arrange a queue for a plurality of priority classes for determining the start priority of each input/output unit. At execution of a start instruction, the central processor sets a control information of the input/output unit to an associated storage area of the main storage and updates the queue arrangement information. The external data controller starts an input/output unit registered to a queue having the highest priority. The start operation is achieved according to the control information of the input/output unit stored in the main storage.

Priority control architecture for input/output operation

An apparatus transfers data between a plurality of input/output (I/O) devices and a main storage unit and includes a plurality of channel devices and a channel control unit. Each channel device is provided with a first data buffer for holding data to be transferred to and transferred from an I/O device. The channel control unit has an address register and a second data buffer. An address register is provided for each channel device, and holds an address of the main storage unit at which address the data to and from the I/O device is stored, and the second data buffer holds the data to be transferred to and transferred from the I/O device, which data is accessed based on the address designated by the address register. A data bus is connected between the first and second data buffers, the data bus having a bit capacity larger than that for data transfer between the I/O device and the channel device.

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Hadano, Japan

Tetsuji Ogawa