Panasonic Corporation

Matsushita Electric Industrial Co., Ltd.

Panasonic Intellectual Property Management Co., Ltd.

Socionext Inc.

Tetsuji Mochida

Tokuzo Kiyohara

Takashi Yamada

Nobuyuki Ichiguchi

Takaharu Tanaka

Ryuta Nakanishi

Koji Asai

Daisuke Imoto

Hideshi Nishida

Makoto Hirai

Kosuke Yoshioka

Takahiro Kamai

Mikio Morioka

Taketoshi Nakao

Ryo Ishida

Hiroyuki Oka

He Cai

Wataru Ohkoshi

A translation device is configured to acquire utterance spoken by a speaker in a first language and translate contents of the utterance into a second language for information presentation, and includes an input unit, a controller, a notification unit, and a storage. The input unit acquires the utterance in the first language and generates voice data from the utterance. The controller acquires a first evaluation value. The notification unit presents the speaker with information on utterance reinput request. The notification unit presents first information on utterance reinput request when the first evaluation value is less than or equal to a first predetermined value. The controller generates new voice recognition data with reference to the past voice recognition data and voice recognition data of reinput utterance, when the voice recognition data of the reinput utterance has an evaluation value less than or equal to a predetermined value.

Translation device and system with utterance reinput request notification

A translation device includes an input unit configured to receive an input sentence in an original language, a controller configured to generate a first translation sentence obtained by translation of the input sentence into a first language, and a display. The controller generates a second translation sentence obtained by translation of the input sentence into a second language different from the first language, a first reverse translation sentence obtained by reverse translation of the first translation sentence into the original language, and a second reverse translation sentence obtained by reverse translation of the second translation sentence into the original language. The controller calculates first similarity as similarity between the first reverse translation sentence and the input sentence, and determines, in accordance with the first similarity, whether to display the first translation sentence on the display or to generate a third translation sentence obtained by translation of the second reverse translation sentence into the first language.

Determining translation similarity of reverse translations for a plurality of languages

A command processing apparatus that processes a plurality of commands which are issued independently from a first master and a second master is provided. The command processing apparatus sequentially issues commands to a storage apparatus including a plurality of banks. The first master issues a first command and a second command in order to the command processing apparatus, with the first command being a command to request access to a first bank and the second command being a command to request access to a second bank different from the first bank. When the second master issues a third command to the command processing apparatus during an interval between issuance of the first command and the second command, the command processing apparatus issues the second command to the storage apparatus consecutively after the first command by prioritizing the second command over the third command.

Command processing apparatus, method and integrated circuit apparatus

A command processing apparatus and method are provided for optimally processing commands issued asynchronously from a plurality of masters to a storage apparatus including a plurality of banks, where each master issues commands for a bankand a bankalternately. The command processing apparatus includes buffer units that obtain commands issued from the plurality of masters, an arbitration unit that arbitrates the obtained commands, and an issuance unit that issues commands to the storage apparatus according to the arbitration. The arbitration unit reads the commands of the plurality of masters obtained in the buffer units, and selects one command as a result of arbitration. The arbitration unit waits until a next command of a master relating to the selected command becomes readable, and reads the next command. The issuance unit consecutively issues the selected command and the read command to the storage apparatus.

A processing device processes data with use of one or more data blocks shared with a plurality of external processing devices. The device includes a processor, and a shared data storage unit that stores, respectively in one or more storage areas thereof, one or more data blocks to be shared with one or more external processing devices. An output unit outputs, when the processor makes an access request to write data in a part of one of the data blocks, a block identifier identifying the one of the data blocks, and the data pertaining to the access request. An input unit judges whether to share external data outputted from one of the external processing devices, based on a block identifier outputted from the one of the external processing devices, and only when judging affirmatively, causes the shared data storage unit to store the external data.

Processor, processing system, data sharing processing method, and integrated circuit for data sharing processing

A memory controller () according to this invention includes: a command generation unit () which generates access commands each including a physical address, based on an access request including a logical address indicating a rectangular area in image data; and a command issuance unit () which issues, to a memory (0), the access commands generated by the command generation unit (). The command generation unit () includes a group determination unit () which determines a group to which a bank including data to be accessed belongs, based on the physical address corresponding to the access request. The command generation unit () generates a pair of a first and a second access commands which share a prefetch buffer between two banks belonging to different groups, when data to be accessed is continuous across two banks belonging to different groups.

Memory controller, memory system, semiconductor integrated circuit, and memory control method

The memory control device according to the present invention includes a command generating unit which divides the memory access request issued by the master into access commands each of which is for one of the memory devices, a command issuing units which issue each of the access commands to the memory devices, a data control unit which switches data between a master and memories, and the command generating unit switch between control for outputting an identical physical address to the memory units and control for outputting different physical addresses to the memory devices, depending on when the physical addresses of the memory devices are identical and when the physical addresses of the memory devices are different, each of the memory devices corresponds to one of the divided access commands.

Memory control device, memory device, and memory control method

In a device, in which a master that requires access at a predetermined rate and a processor that requires responsiveness to an access request access a shared memory, responsiveness to the access request of the processor is improved while the access of the master at the predetermined rate is guaranteed, compared to conventional technologies. When the master has a resource available for accessing the shared memory, the master accesses the shared memory at the predetermined rate or above. When the access is executed at the predetermined rate or above, the processor accesses the shared memory by using a resource that was originally allocated to the master.

Access control device, access control integrated circuit, and access control method

The information processing device in the present invention includes a memorywhich is a DRAM featuring a burst mode, and burst-transfers data at successive column addresses, masters (), (), and () which issue access requests, and a command processing unit () which converts an access address that is included in the access request issued from each master. One or more of the masters access an M&#xd7;N rectangular area where M and N are integers, and the command processing unit () converts access addresses so that a column address of data at the (K+m)th column, where K and m are integers and m&#x2266;M, of an Lth line, and a column address of data at a Kth column of an (L+n)th line, where L and n are integers and n&#x2266;N, become successive.

Burst memory access method to rectangular area

An arbitration device arbitrates among master devices such that each master device is allowed to access a shared memory at a predetermined bandwidth, and the arbitration device permits an access request in a first period that a designer has set as desired if the access request has been made by a specific master device beyond a bandwidth that has been allocated in advance. The arbitration device masks an access request from the specific master device in a second period that follows the first period.

Arbitration device for arbitrating among a plurality of master devices, arbitration method, and video processing device including the arbitration device

A transcoder for resizing video data and outputting the resized video data to a reproduction apparatus. The reproduction apparatus reproduces the resized video data by repeating a display period and a non-display period alternately. The transcoder includes: a resizing unit that resizes the video data; and a control unit that causes the resizing unit to resize the video data to first video data having a first resolution so that the reproduction apparatus displays one image during each display period, and causes the resizing unit to resize, during each period between the resizing of the video data to the first video data, the video data to second video data having a second resolution that is lower than the first resolution.

Transcoder

In a resource request arbitration apparatus according to the present invention, a request masking unit masks a memory access request REQ that is issued by a resource requesting device at over a minimum frequency needed for the resource requesting device, and an arbitrating unit acknowledges one of the memory access requests RREQ that are not suspended by the request masking unit, based on a predetermined static order of priority. With this resource request arbitration apparatus, the arbitrating unit do not have to concern anything other than the predetermined priority order among the memory access requesting units, and an easy and plain arbitration system based on the static priority order ensures the minimum frequency for acknowledging the resource requests that each memory access requesting unit needs.

Apparatus, method, and computer program for resource request arbitration

When an OSD data storage area for storing OSD data needs to be reserved, an area of a frame storage apparatus that should store macroblocks corresponding to an invisible area on a screen is allocated as the OSD data storage area. There is no degradation in picture quality. When doing so, the data reduction control unit receives an instruction to reserve the OSD data storage area and discards the corresponding macroblocks. The OSD data access unit writes the OSD data into an area of the frame storage apparatus that was assigned to store the discarded macroblocks.

IMAGE DECODING APPARATUS THAT PERFORMS IMAGE DECODING SO THAT FRAME AREAS THAT OCCUPY A LARGE AREA IN A STORAGE APPARATUS CAN BE USED FOR OTHER PURPOSES, AND A RECORDING MEDIUM RECORDING AN IMAGE DECODING PROGRAM

Growing community of inventors

Osaka, Japan

Tetsuji Mochida