Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Tetsuji Kishi

Ichiro Okabayashi

Yuri Kuwata

Yasuhiro Mori

Minoru Okamoto

Daisuke Murakami

Manabu Migita

Seiji Horii

Katsuhiko Ueda

Atsushi Nagata

Yuji Takai

Shirou Yoshioka

Yoshiharu Watanabe

Takahide Baba

Atsushi Kotani

Yoshimichi Nagasaki

A terminal device transmits device information thereof and a request for acquiring information contents to a contents distribution device. The contents distribution device generates a request for distributing a program for materializing the information contents in the terminal device based on the information contents designated in the acquisition request and the device information, and transmits a license request for using a function standard required for realizing the function to a license management device. The license management device receives the usage license request and correspondingly transmits an authorization for using the function standard to the program distribution device and the contents distribution device. The program distribution device transmits the program to the terminal device only when the usage authorization is received. The contents distribution device transmits the information contents to the terminal device only when the usage authorization is received.

Information contents download system

A resource management device of the present invention, used in a system where at least one bus master is connected to each of a plurality of buses, includes: a bus arbitration section for arbitrating an amount of access to be made from the buses to a shared resource; an arbitration information management section for managing, as bus arbitration information, a bus priority order and a highest access priority pattern for ensuring a predetermined access bandwidth to the shared resource for each bus for an arbitration operation by the bus arbitration section; and a resource control section for controlling, based on characteristics of the shared resource, an access to the shared resource from the bus whose access request has been granted by the bus arbitration section. Thus, it is possible to guarantee a minimum bandwidth for access to the shared resource for each of the plurality of bus masters.

Resource management device for managing access from bus masters to shared resources

The rendering performance of a graphic processor is improved by effectively using a data bus. An externally-input graphics command is stored in a work memory via the data bus. A display data generation section receives a graphics command stored in the work memory via the data bus, decodes the received graphics command, and outputs the display data to the data bus. An image display section receives display data stored in the work memory via the data bus, and displays an image on a display device. A bus control section monitors the status of use of the data bus, and controls the right to use the data bus according to the priority of each data transfer operation.

Graphic processor and graphic processing system

An inventive line-drawing apparatus draws a line that connects a start point to an end point. The start and end points are both presented on a display and represented by mutually different sets of coordinates. The apparatus includes first and second FIFO memories, an adder and a shifter. Each of the first and second FIFO memories accepts a plurality of input coordinate data and sequentially outputs one of these data after another on a first in, first out basis. The adder receives and adds together the respective coordinate data output from the first and second memories and outputs added data. And the shifter divides the added data by two and outputs divided data. The coordinate data output from the first and second memories are input to the first memory. The divided data is input from the shifter to the second memory. The line connecting the start and end points together is drawn on the display in accordance with the divided data output from the shifter.

Apparatus and method for drawing lines

An image processor, included in a logic circuit unit, for executing an image processing of data according to the MPEG standard and the like, a memory circuit unit, whose input port is included in the logic circuit unit, for storing image processed data, and a memory control unit, included in the logic circuit unit, for controlling the input/output operation of the memory circuit unit are formed on a semiconductor substrate. Between the memory circuit unit and the memory control unit, a selector is interposed for selecting, in accordance with a test mode signal, an externally input first chip select control signal when the test mode signal is activated, and selecting a second chip select control signal output by a memory control circuit and outputting a chip select signal to the memory circuit unit when the test mode signal is deactivated.

Semiconductor integrated circuit device capable of simultaneously

A test unit for testing a random logical circuit and a functional macrocircuit according to a scan test mode signal and a macro test mode signal is provided. The test unit includes a first and a second bidirectional I/O module. Whereas the first bidirectional I/O module is a module for providing a macro test output signal outside or providing a scan test input signal to the random logical circuit, and in addition, for performing input/output processing of a first normal input signal and a first normal output signal with respect to the random logical circuit, the second bidirectional I/O module is a module for providing a macro test input signal to the functional macrocircuit or providing a scan test output signal outside, and in addition, for performing input/output processing of a second normal input signal and a second normal output signal with respect to the random logical circuit.

Semiconductor integrated circuit

In a system for executing distribution, arrangement and collection of array data between a host processor and plural processor elements, control parameter regarding array data to be transferred and an identification number assigned to each data receiver are set beforehand to a data receiver of each processor element. Data sequentially sent out onto a data bus with synchronization with a strobe signal from the data transmitter of the host processor are fetched selectively according to a data transfer allowance signal generated based on the control parameter and the identification number. The fetched data is written into a memory with a discrete address.

Data transfer device and multiprocessor system

One data transmitter for transmitting a broadcast data onto an outside data bus and data receivers, whose number is 'n', for individually receiving the transmitted broadcast data are provided. A single error signal line is connected in common to the data transmitter and each of the 'n' data receivers. Each of the data receivers notifies an error detection to the data transmitter and the other data receivers via the error signal line with a wired OR connector when its own data receivers detects an error. Being notified of the error detection, the data transmitter re-transmits the data so that all of the data receivers re-receive the data. Accordingly, re-transfer per one data at a broadcast transfer is contemplated.

High speed data transfer device having improved efficiency

There are provided a data transmitter for sequentially transmitting data to which error correcting codes are added, and a data receiver for returning a retransmission request signal if the received data has errors which cannot be corrected. The data transmitter does not confirm that the retransmission request signal related to the transmitted data is received and data are consecutively transmitted from a FIFO memory in a pipeline fashion while holding the transmitted data in a data latch. The data receiver sequentially stores the received data in the FIFO memory on a receiving end in a pipeline fashion. In the case where the retransmission request signal is transmitted from the data receiver, the data transmitter immediately transmits retransmission data which has been prepared in the data latch.

Growing community of inventors

Osaka, Japan

Tetsuji Kishi