Matsushita Electric Industrial Co., Ltd.

Tetsuji Gotoh

Keiichi Kusumoto

Tomoyuki Kumamaru

Takashi Andoh

In a static circuit or the like, upper and lower terminals are both set to a first power supply potential Vdd in the operating state of an inverter circuit. In the non-operating state, the power supply potential of the upper terminal is reduced to a second power supply potential Vdd (<<Vdd ). Provided that an input signal of the inverter circuit has a potential Vdd (H level), an output signal thereof must be held at the ground potential (L level) in the operating state. This requires that a conductance Gp of a PMOS transistor and a conductance Gn of a NMOS transistor satisfy the relation: Gp<Gn. Therefore, a well terminal (lower terminal) of the PMOS transistor is set to a potential higher than the power supply potential Vdd in order to maintain the relation: Gp<Gn. Accordingly, a signal determined by the circuit in the operating state can be held even in the non-operating state, and the power supply voltage is set to an extremely low potential in the non-operating state of the circuit.

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Osaka, Japan

Tetsuji Gotoh