Renesas Technology Corp.

Mitsubishi Denki Kabushiki Kaisha

Tetsuichiro Ichiguchi

Tadaaki Yamauchi

Makoto Suwa

Junko Matsumoto

Takeo Okamoto

Zengcheng Tian

Hideki Yonetani

Tsutomu Nagasawa

A manner of generating internal voltages such as a high voltage, an intermediate voltage and an internal power supply voltage is switched in accordance with a power supply level setting signal. When the voltage level of an external power supply voltage is low, a current drive transistor receiving an output of a comparing circuit and an auxiliary drive transistor are forcedly set in a conductive state, and external power supply voltage is transmitted on an internal power supply line. At this time, the comparing operation of the comparing circuit is stopped. When the level of the external power supply voltage is high, the comparing circuit is activated down convert the external power supply voltage for generating a peripheral power supply voltage on the internal power supply line.

Semiconductor device having internal voltage generated stably

Data pad regions are arranged in four divided regions of a semiconductor memory chip of a rectangular shape, respectively, and data pads are selectively utilized in each of the four divided regions in accordance with a word structure. Thus, it is possible to implement a semiconductor memory chip capable of being assembled in both a single chip package and a multi chip package.

Semiconductor circuit device adaptable to plurality of types of packages

The semiconductor memory device includes a refresh timer for determining a refresh cycle of self-refresh operation. The refresh timer includes a voltage regulator, a ring oscillator and a counter. The voltage regulator generates a bias voltage having positive temperature characteristics. The ring oscillator varies an oscillation cycle of a pulse signal according to the bias voltage. The counter counts a prescribed number of pulse signals and generates a refresh signal for executing refresh operation. The semiconductor memory device thus varies the refresh cycle according to a temperature change, and executes refresh operation with an appropriate refresh cycle.

Semiconductor memory device requiring refresh operation

A row address decoder of a semiconductor memory device generates internal row address signals RAD< and /RAD< > by switching most significant bit and least significant bit of row address signals RA< > and /RA< > that correspond to address signals A to A , respectively. In a twin cell mode, the least significant bits RAD< > and /RAD< > of the internal row address signals corresponding to the most significant bits RA< > and /RA< > of the row address signal that are not used are selected simultaneously by row address decoder, and two adjacent word lines are activated simultaneously. Consequently, the configuration of memory cell in the semiconductor memory device can electrically be switched from the normal single memory cell type to the twin memory cell type.

Semiconductor memory device switchable to twin memory cell configuration

A clock buffer of a DRAM includes: a first NAND gate which is driven by a first internal power supply voltage (2.5 V) and which determines the level of an input clock signal if the DRAM is used for a TTL-system interface (MLV&equals;2.5 V); and a second NAND gate which is driven by a second internal power supply voltage (1.8 V) and which determines the level of the input clock signal if the DRAM is used for a 1.8 V-system interface (MLV&equals;0 V). Accordingly, in each of the first and second NAND gates, sizes of four MOS transistors can be set at optimum values, respectively.

Semiconductor device used in two systems having different power supply voltages

A word line drive signal generating circuit, which generates a word line drive signal RX to a selected word line, includes an RX generating circuit responsive to an external row address strobe signal *RAS (or/RAS) for generating word line drive signal RX, a determination circuit responsive to an operating power supply voltage level or an externally applied signal for determining whether the word line drive signal RX should be boosted up, and a boosting circuit responsive to the word line drive signal RX and an output of determination circuit for boosting up the word line drive signal RX. The word line drive signal RX is boosted up to or above the operating power supply voltage level only when the determination circuit determines it to be necessary. Thereby, a high voltage is not normally applied to the word line, so that deterioration of breakdown voltage of the word line is prevented, and the reliability of the word line is improved.

Semiconductor memory device with complete inhibition of boosting of word

A dynamic random access memory comprises memory cells (MA1-Man) and sense amplifies (SA1-SAn) in a memory array region III and memory cells (MB1-MBn) and sense amplifies (SB1-SBn) in a memory array region IV. In reading operation, first, the sense amplifiers in one region comprising a memory cell designated by an address signal are activated and then sense amplifiers in the other region are activated. As a result, since amplifying operation by the sense amplifiers is performed sequentially, a peak value of a current consumed by the amplification can be reduced.

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Hyogo, Japan

Tetsuichiro Ichiguchi