Samsung Display Co., Ltd.

Tetsuhiro Tanaka

Ki Seong Seo

Hee Won Yoon

Yeong-Gyu Kim

Jung Yub Seo

Wonsuk Choi

Seokje Seong

Seungwoo Sung

Jiseon Lee

Seung Hyun Lee

Jiryun Park

Young-in Hwang

Chang Ho Yi

Shin Beom Choi

Hyun Min Cho

Jae Hoon Lee

Seung-Hwan Cho

Seunghyun Lee

Hai Jung In

Byung Ki Chun

Seok Je Seong

Seung-hwan Cho

Tae Sik Kim

Yoon-Jong Cho

Kiseong Seo

Jonghyun Yun

Sug Woo Jung

Hee Yeon Kim

Dae Seop Kim

Kyeong Woo Jang

Yeong Gyu Kim

Jung Woo Ha

A display device may include first pixels disposed in a display area and including respective first driving transistors. A second pixel is disposed in a non-display area and includes a second driving transistor. A sensor is configured to sense a current of the second pixel during a sensing period and generate sensing data. A degradation compensator is configured to convert first image data into second image data. A data driver is configured to generate data signals based on the second image data and supply the data signals to the first pixels. The degradation compensator calculates an age of the first pixels based on accumulating the second image data, converts the first image data into the second image data by deriving a compensation value from representative compensation data according to the age of the first pixels, and calibrates the representative compensation data based on the sensing data.

Display device and method of compensating for degradation thereof

A display panel includes a first organic film layer, a first barrier layer disposed on first organic film layer, a shielding pattern disposed on the first barrier layer, a second barrier layer covering the shielding pattern and disposed on first barrier layer, a first active pattern disposed on the second barrier layer and overlapping the shielding pattern in a plan view, a gate electrode disposed on the first active pattern, an emission control line disposed on the first active pattern and adjacent to a first side of the gate electrode in the plan view, an upper compensation control line disposed on the emission control line and adjacent to a second side of gate electrode in the plan view, and a second active pattern disposed on the emission control line.

Display panel including active pattern overlapping shielding pattern, and display device including the same

A display device includes a semiconductor layer on an opposite side to a light-blocking layer, the semiconductor layer including an active layer overlapping the light-blocking layer, a first gate insulator on an opposite side to a buffer film with the active layer therebetween, and a first gate electrode on an opposite side to the active layer with the first gate insulator therebetween, a side surface of the first gate insulator includes a first inclined portion contacting a first surface of the semiconductor layer, and a second inclined portion contacting the first inclined portion and the first gate electrode, and a first angle between the first surface of the semiconductor layer and the first inclined portion is less than a second angle between the first surface of the semiconductor layer and the second inclined portion.

Display device

A display device includes a first active pattern disposed on a substrate, a first gate electrode disposed on the first active pattern, a second active pattern disposed on the first gate electrode, being electrically connected to the first gate electrode, and including an extension part extending in a first direction and a protrusion part protruding from the extension part in a second direction crossing the first direction, and a voltage line disposed on the second active pattern, extending in the first direction, and overlapping the protrusion part in an overlapping region. The voltage line contacts the protrusion part through a first contact, and the first contact entirely overlaps the overlapping region on a plane.

Display device with voltage line contact

A display device comprises a base substrate, a lower interlayer dielectric layer, an oxide semiconductor layer including a first channel region, a first drain region disposed on one side of the first channel region, and a first source region, a first gate insulating layer, a first upper gate electrode, an upper interlayer dielectric layer, and a first source electrode and a first drain electrode, wherein the lower interlayer dielectric layer includes a first lower interlayer dielectric layer disposed on the base substrate, and a second lower interlayer dielectric layer disposed on the first lower interlayer dielectric layer, wherein the first lower interlayer dielectric layer includes silicon nitride and the second lower interlayer dielectric layer comprises silicon oxide, and wherein a composition ratio of nitrogen to silicon in the first lower interlayer dielectric layer ranges from 0.8 to 0.89.

A display device includes a base substrate; an oxide semiconductor layer disposed on the base substrate; a first gate insulating layer disposed on a first channel region of the oxide semiconductor layer and that overlaps the first channel region thereof; a first upper gate electrode disposed on the first gate insulating layer; and an upper interlayer insulating layer disposed on the first upper gate electrode, the first upper gate electrode, and the oxide semiconductor layer, wherein the upper interlayer insulating layer includes a first upper interlayer insulating layer, a second upper interlayer insulating layer, and a third upper interlayer insulating layer, the first upper interlayer insulating layer includes silicon oxide, each of the second and third upper interlayer insulating layers include silicon nitride, and a hydrogen concentration in the second upper interlayer insulating layer is less than a hydrogen concentration in the third upper interlayer insulating layer.

Display device and method of manufacturing the same

A display device may include a first active layer disposed on a substrate, a scan line disposed on the first active layer, a lower gate signal line disposed on the scan line, an oxide semiconductor pattern disposed on the lower gate signal line, and including a channel part that overlaps the lower gate signal line and a low-resistance part formed on a side portion of the channel part, a metal pattern disposed on at least one surface of the low-resistance part, and an upper gate signal line disposed on the oxide semiconductor pattern to overlap the channel part.

Display panel including gate lines on opposite sides of a shielding pattern, and display device including the same

A display device includes a first thin film transistor disposed on a substrate. A first insulating interlayer covers the first thin film transistor. An active pattern is disposed on the first insulating interlayer. The active pattern includes indium-gallium-zinc oxide (IGZO) having a thickness in a range of about 150 &#x212b; to about 400 &#x212b;. A gate insulation layer covers the active pattern. A gate pattern is disposed on the gate insulation layer. A second insulating interlayer covers the gate pattern.

A display device includes a polycrystalline semiconductor including a channel, a first electrode, and a second electrode of a driving transistor, a first gate insulating layer, a gate electrode of a driving transistor, a first electrode of a boost capacitor, a second gate insulating layer, a first interlayer insulating layer, an oxide semiconductor including a channel, a first electrode, and a second electrode of a second transistor, a channel, a first electrode, and a second electrode of a third transistor, and a second electrode of a boost capacitor, a third gate insulating layer disposed on the oxide semiconductor, a gate electrode of the second transistor overlapping the channel of the second transistor, a gate electrode of the third transistor overlapping the channel of the third transistor, and a second interlayer insulating layer disposed on the gate electrode of the second transistor and the gate electrode of the third transistor.

Growing community of inventors

Hwaseong-si, South Korea

Tetsuhiro Tanaka