Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Tetsuhiko Azuma

Satoshi Kaburaki

Konosuke Watanabe

Takuya Haga

A first memory stores a translation table indicating a first correspondence between a logical address and a physical address at first timing. A second memory stores a difference table that is configured to record, in each of entries, a correspondence between a logical address range and a physical address range, the correspondence representing a difference between the first correspondence and a second correspondence. The second correspondence is between the logical address and the physical address at second timing. In non-volatilizing data in a first logical address range to a first physical address range, in a case where the entries includes a first entry containing a correspondence between a second logical address range and a second physical address range, the controller updates the first entry. The first logical address range follows the second logical address range, and the first physical address range follows the second physical address range.

Memory system

According to one embodiment, there is provided a bus access controller including a memory, multiple buffers, and an issuance circuit. Information necessary for bus access can be set in the memory. The multiple buffers store information set in the memory. The issuance circuit is connected to a bus. The issuance circuit issues a bus-access instruction, according to information stored in a buffer selected from among the multiple buffers in response to a request.

Bus access controller, hardware engine, controller, and memory system

According to one embodiment, a memory system includes a nonvolatile memory, a device controller, and a tag memory. The device controller stores a part of a logical-to-physical address translation table (L2P table) stored in the nonvolatile memory in a memory of a host as a cache. The tag memory includes a plurality of entries associated with a plurality of cache lines of the cache. Each entry includes a tag indicating which area of the L2P table is stored in a corresponding cache line, and a plurality of bitmap flags indicating whether a plurality of sub-lines included in the corresponding cache line are valid or not.

Memory system and information processing system

An embodiment of pulse width modulated (PWM) signal generator includes a module or modules to calculate an amount of change in a period length and duty ratio of an output signal during a transition period between a first signal waveform and a second signal waveform using a first period parameter, a second period parameter, and a parameter indicating a predetermined number of steps in the transition period. The period parameter and duty parameter of the output signal during the steps of the transition period are based on the calculated amounts of change.

Pulse width modulation signal generator

A data transfer device which controls data transfer between a first memory device and a second memory device, includes a first transfer arbiter circuit and a second transfer arbiter circuit. The first transfer arbiter circuit outputs, in response to a transfer instruction for transfer of data from the first memory device to the second memory device, first transfer instructions to transfer data in a first transfer unit in an order of addresses. The second transfer arbiter circuit outputs, in response to the first transfer instruction, second transfer instructions to transfer the data of the first transfer unit in a second transfer unit smaller than the first transfer unit. The second transfer arbiter circuit outputs the second transfer instruction in an order of accessible addresses in the first and second memory devices.

Data transfer device which executes DMA transfer, semiconductor integrated circuit device and data transfer method

A cache memory system includes a cache memory having a plurality of entries associated with a plurality of information storage units. Each of the information storage units is configured to store part of the information stored in a main memory. Reference bit storage units store a use status of entry data for a certain period of time. A hit detection circuit is connected to the information storage units. The hit detection circuit generates a hit signal to each of the reference bit storage units when the entry data is determined to satisfy use conditions.

Cache memory system and method using reference bits

An aspect of the present invention provides a microprocessor that includes a processor core including an instruction executing unit configured to execute instructions for input and output controlling and processing for data and a cache memory configured to store the data, a memory management unit coupled to the processor core, the memory management unit configured to manage memory system including the cache memory, and a bus interface coupled to the processor core and the memory management unit, the bus interface configured to rearrange the bits of the data transferred from the processor core.

Microprocessor and video/sound processing system

A signal processor including a processor having a cache memory and a process execution unit executing a process by use of information temporarily stored in the cache memory and an external memory provided external to the processor. In the signal processor, the process execution unit automatically returns to a start point of a loop-type data at an end of the loop-type data and sequentially reads out the loop-type data from the external memory to the cache memory.

Growing community of inventors

Yokohama, Japan

Tetsuhiko Azuma