Fujitsu Corporation

Tetsuaki Wakabayashi

Shiro Uriu

Naoki Matsuoka

Hiroshi Tomonaga

Kenichi Okabe

Tsuguo Kato

Kenichi Kawarai

Kazumasa Sonoda

Masakatsu Nagata

Masanobu Furukoshi

The packet switch performs a scheduling process by selecting a unicast packet or a multicast packet to be output from each of N input buffers such that input lines and output lines cannot conflict each other for a unicast packet, and such that the input lines cannot conflict each other for the multicast packet.

Packet switch

A switching apparatus that is used for high-speed large-capacity routing and a communication apparatus and communication system that are used for an efficient recursive multicast. A matrix switch performs self-routing on a packet on the basis of a tag including output route information set in the packet. Selectors are located so as to correspond to N output ports P#through P#N of the matrix switch and perform N-to-one selection control. Setting registers hold selection information used by the selectors to select a signal.

Switching apparatus, communication apparatus, and communication system

In a common buffering device with a simple arrangement, a write address can be efficiently released from a buffer memory upon receipt of a multi-address call. For an ATM cell which is to be transmitted to a specific line, a write address is set in a common buffer memory, and the ATM cell is written at the write address. The ATM cell is read from an address which corresponds to the write address, and is transmitted to the specific line. Then, the pertinent write address is released. In a write table are entered a plurality of multi-address lines across which an ATM cell written at a specific address in the common buffering device can be multicast. Each time the ATM cell is read from the specific address, a designation line for transmission of an ATM cell in a read control table is compared with the multi-address lines set in the write control table. When the lines match, the write address for the ATM cell, which is set in the write control table, is released.

Address release method, and common buffering device for ATM switching system which employs the same method

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Kawasaki, Japan

Tetsuaki Wakabayashi