Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Vlsi Engineering Corporation

Tetsu Udagawa

Kazumasa Yanagisawa

Masamichi Ishihara

Kazuhiko Kajigaya

Yasuhiro Kasama

Kyoko Ishii

Yutaka Kobayashi

Makoto Yoshida

Yasushi Takahashi

Goro Kitsukawa

Hitoshi Miwa

Kazuyoshi Oshima

Seiji Narui

Atsushi Nozoe

Masayuki Nakamura

Tetsurou Matsumoto

Takashi Shinoda

Shoji Wada

Yoshitaka Kinoshita

Tatsuyuki Ohta

Hiromi Tsukada

Yoshiaki Ouchi

Kazuo Mihashi

Gen Murakami

Ichiro Anjoh

Takashi Yamazaki

Hiroaki Kotani

Hiroshi Satoh

Yasunori Yamaguchi

Toshiyuki Sakuta

Eiji Miyamoto

Kazuya Ito

Satoshi Oguchi

Youichi Matsuno

Atsusi Nozoe

Kiyoo Itoh

Masashi Horiguchi

Masakazu Aoki

Jun Etoh

Manabu Tsunozaki

Shin'ichi Ikenaga

The sheet resistance of a gate electrodeA (a word line) of memory cell selection MISFET Q a DRAM and a sheet resistance of bit lines BL, BLare, respectively, 2 &#x3a9;/&#x25a1; or below. Interconnections of a peripheral circuit are formed during the step of forming the gate electrodeA (the word line WL) or the bit lines BL, BLby which the number of the steps of manufacturing the DRAM can be reduced.

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE INCLUDING MEMORY CELL SECTION HAVING CAPACITOR OVER BITLINE STRUCTURE AND WITH THE MEMORY AND PERIPHERAL SECTIONS HAVING CONTACT PLUG STRUCTURES CONTAINING A BARRIER FILM AND EFFECTING ELECTRICAL CONTACT WITH MISFETS OF BOTH MEMORY AND PERIPHERAL SECTIONS

The sheet resistance of a gate electrode A (a word line) of memory cell selection MISFET Q a DRAM and a sheet resistance of bit lines BL , BL are, respectively, 2 &OHgr;/&square; or below. Interconnections of a peripheral circuit are formed during the step of forming the gate electrode A (the word line WL) or the bit lines BL , BL by which the number of the steps of manufacturing the DRAM can be reduced.

Semiconductor integrated circuit device and method for manufacturing the same

The sheet resistance of a gate electrode 8A (a word line) of memory cell selection MISFET Q of a DRAM and a sheet resistance of bit lines BL.sub.1, BL.sub.2 are, respectively, 2 .OMEGA./.quadrature. or below. Interconnections of a peripheral circuit are formed during the step of forming the gate electrode 8A (the word line WL) or the bit lines BL.sub.1, BL.sub.2 by which the number of the steps of manufacturing the DRAM can be reduced.

Semiconductor integrated circuit device and method for manufacturing the

An ordinary read/write operation (normal operation) and a refresh operation are separated from one another and the number of read amplification circuits or, in other words, the number of sense amplifiers operating during the normal operation is made smaller than that during the refresh operation. Accordingly, a bit line charge/discharge current during the normal operation can be reduced.

Dynamic type semiconductor memory device

An ordinary read/write operation (normal operation) and a refresh operation are separated from one another and the number of read amplification circuits or in other words, the number of sense amplifiers operating during the normal operation is made smaller than that during the refresh operation. Accordingly, a bit line charge/discharge current during the normal operation can be reduced.

Semiconductor memory having both a refresh operation cycle and a normal

Semiconductor memory having a refresh operation cycle and operating at a

A pair of DRAM chips 1A and 1B are mounted opposedly to each other with wiring means such as lead frames put therebetween, the lead frames being substantially integral with external terminals 3B. Then, these DRAM chips and lead frames are connected together by the conventional wire bonding method. Plural pairs of the thus-connected DRAM chips and lead frames are stacked and corresponding leads of the lead frames are connected in common to form a laminate. The plural DRAM chips thus mounted are activated selectively in accordance with a predetermined chip selection signal. Additionally, partial DRAM chips capable of partially functioning normally are combined together by utilizing the above chip mounting method to constitute a single DRAM package.

Sealed stacked arrangement of semiconductor devices

A Bi.CMOS semiconductor memory device is provided which includes an arrangement to simultaneously select a plurality of memory cells, followed by using a 3 bit Z addressing arrangement to determine a read or write operation for the simultaneously selected memory cells. To speed up the word line selection, a static selection type operation is used with the word line selecting voltage being greater than signal amplitude of the data lines during the write operation. Also, to speed up the read operation, separate common I/O lines are provided for the read and write operations. Read signals are transmitted as current signals, and then converted to voltage signals for improving reading speed. Also, improved arrangements are provided for resistance structure, logic circuitry, input circuitry, fuse cutting circuitry, drive circuitry, power circuitry, electrostatic protection circuitry, layout structure and testing methods for the semiconductor device.

Dynamic Random Access Type Semiconductor Device

A voltage conversion circuit of the present invention is equipped with means for generating a first voltage stabilized with respect to ground potential of a semiconductor integrated circuit device including the circuit, means for generating second voltage stabilized with respect to an external supply voltage of the semiconductor integrated circuit device, and selection means for selecting either the first voltage or the second voltage. The first voltage age, stabilized with respect to the ground potential, is selected and used as the voltage at the time of normal operation, and the second voltage, stabilized with respect to the external supply voltage, is selected and used at the time of aging test. In this case, means for trimming the first voltage and/or the second voltage is, preferably, provided to raise the voltage accuracy.

Semiconductor IC device having a voltage conversion circuit which

A pair of DRAM chips 1A and 1B are mounted opposedly to each other with wiring means such as lead frames put therebetween, the lead frames being substantially integral with external terminals 3B. Then, these DRAM chips and lead frames are connected together by the conventional wire bonding method. Each chip is bonded with an associated lead frame and each lead frame is disposed as plural lead frame conductors contacting mutually lead frame conductors associated with similarly function bonding pads, i.e. external terminals of the chips, of the other one of the pair of chips. Ones or plural pairs of the thus-connected DRAM chips and lead frames are stacked and corresponding leads of the lead frames are connected in common to form a laminate. The plural DRAM chips thus mounted are activated selectively in accordance with a predetermined chip selection signal. Additionally, partial DRAM chips capable of partially functioning normally are combined together by utilizing the above chip mounting method to constitute a single DRAM package.

Multi-chip semiconductor package

Testing method for a semiconductor memory device

A Bi.CMOS semiconductor memory device is provided which includes an arrangement to simultaneously select a plurality of memory cells, followed by using a 3 bit Z addressing arrangement to determine a read or write operation for the simultaneously selected memory cells. To speed up the word line selection, a static selection type operation is used with the word line selecting voltage being greater than signal amplitude of the data lines during the write operation. Also, to speed up the read operation, separate common I/O lines are provided for the read and write operations. Read signals are transmitted as curent signals, and then converted to voltage signals for improving reading speed. Also, improved arrangements are provided for resistance structure, logic circuitry, input circuitry, fuse cutting circuitry, drive circuitry, power circuitry, electrostatic protection circuitry, layout structure and testing methods for the semiconductor device.

Bi-CMOS semiconductor memory device, including improved layout structure

A memory device is provided including a plurality of memory arrays and peripheral circuits. For example, in a dynamic RAM the peripheral circuitry will include row address decoders, column address decoders, sense amplifiers and main amplifiers disposed in such a manner as to correspond to the memory arrays, respectively. The desired row address decoders, column address decoders, sense amplifiers and main amplifiers are selectively operated in accordance with a common array selection signal generated on the basis of at least part of row address signals. Accordingly, only the row address decoders, column address decoders, sense amplifiers and main amplifiers corresponding to the memory array containing the designated memory cells are operated selectively in accordance with the common array selection signal. It is thus possible to reduce power consumption of the dynamic RAM and to simplify the structure of the peripheral circuits and wirings.

Semiconductor memory device

Growing community of inventors

Iruma, Japan

Tetsu Udagawa