Mitsubishi Denki Kabushiki Kaisha

Tetsu Tashiro

Yoshiki Cho

Kazuo Hayashi

Minoru Takeuchi

Shinichi Hirose

Yoshiyuki Ishimaru

A serial communication circuit which is so configured that the sub CPU SC determines a timing of bit formats with software, specificially, that the sub CPU SC controls a level of each section or an output timing of each signal of one unit to be transmitted of data by writing specific values with software to the specific registers 3, 4, 6, 95 and so on, and also at the time of receiving, the sub CPU SC controls with software a level of each section or a timing of taking in data of each signal of one unit. Thereby, it becomes possible for the serial communication circuit to process protocols of different bit formats only by changing firmware.

Serial communication circuit on an LSI chip and communicating with

A control circuit is provided which enables the main CPU 23 to access a memory space of the sub CPU 1 by means of the test mode control register 4 which can be controlled via the main CPU bus 10. Also a control circuit is provided to branch into a break routine by comparing the value of the program counter 5 of the sub CPU 1 and the value set in the break vector register 7. Further, a control circuit which enables it to reset the sub CPU 1, to branch according to a test vector and to make break branch under the control of the main CPU 23 is provided, thereby making it easy to incorporate the sub CPU 1 on-chip in the conventional single CPU constitution. Thus testing environment and debugging environment for the sub CPU 1 is provided in the microcomputer having a plurality of CPUs on a single chip without connecting the exclusive test terminal of the sub CPU 1 or the sub CPU bus 28 with the outside.

Microcomputer with multiple CPU'S on a single chip with provision for

A high-speed microcomputer having a condition decision circuit in which a signal output indicating whether or not a branch condition is satisfied is always active by taking out only a necessary bit by a mask register value after comparing a register value and a compare register value for every bit.

Condition decision circuit for a microcomputer

A pulse-signal extracting method and apparatus which are capable of generating an accurate pulse output even if the pulse input signal greatly pulsates due to a low-frequency noise component. A predetermined offset voltage is added to the input signal where the low-frequency noise component is superimposed on a pulse waveform which is the signal component so as to obtain an amplified signal. This amplified signal is inputted to a low-pass filter so as to output only the amplified flow-frequency component, and the original input signal is compared with the amplified low-frequency component in a comparator so as to extract the pulse waveform, which is the signal component, on the basis of the comparison result.

Method and apparatus extracting pulse signal

When the reset input changes 0 V to Vcc, predetermined operational mode control information is set in an operational mode register (11) to establish a user operational mode. When the reset input changes from 0 V to 2 Vcc, the operational mode control information inputted to a predetermined terminal of the input/output port (25, 58) is set in the operational mode control unit (10a, 10b) to establish a test or other mode.

Growing community of inventors

Itami, Japan

Tetsu Tashiro