Kabushiki Kaisha Toshiba

Fujitsu Corporation

Toshiba Electronic Devices & Storage Corporation

Tetsu Hasegawa

Masaharu Doi

Chikako Tokunaga

Takashi Shiraishi

Akira Ishii

Takehito Tanaka

Kenichi Anzou

Kazuhiro Tanaka

Tetsuya Miyatake

Koji Urata

According to one embodiment, a semiconductor integrated circuit includes: a logic circuit including a first scan chain configured to operate based on a first clock signal and a second scan chain configured to operate based on a second clock signal in a built-in self-test; a pattern generator configured to generate a test pattern and transmit the test pattern to the first and second scan chains; a compression circuit configured to compress first data received from the first and second scan chains; a clock select circuit configured to select one of the first and second clock signals and transmit the one of the first and second clock signals to the corresponding one of the first and second scan chains in the test; and a test control circuit configured to control the test and detect a fault in the logic circuit based on a result of the test.

Semiconductor integrated circuit, circuit designing apparatus, and circuit designing method

According to one embodiment, a semiconductor integrated circuit includes: a logic circuit including: a first scan chain and a second scan chain; a clock generator; and a test control circuit. The first scan chain includes: a first flip-flop having a first scan data input terminal and a first output terminal; and a first multiplexer. The first multiplexer is configured to electrically couple the first scan data input terminal to the first output terminal based on a first signal received from the test control circuit to form a first closed loop. The second scan chain includes a second flip-flop having a second scan data input terminal and a third output terminal that is not coupled to the second scan data input terminal.

An optical device and an optical transmitter are provided. The optical device includes a substrate, a first optical waveguide that may be formed in the substrate and may have a bending portion, and a second optical waveguide that intersects with the bending portion of the first optical waveguide, wherein a groove may be formed outside the bending portion of the first optical waveguide in the substrate.

Optical device and optical transmitter

An optical modulation device includes: a crystal substrate having an electro-optic effect; an optical waveguide formed in the crystal substrate; an electrode formed on the crystal substrate, to apply an electric field to the optical waveguide; and a buried layer of low dielectric constant buried to avoid the optical waveguide, in at least one portion of a lower region of the electrode inside the crystal substrate, which is spaced from both of a front surface of the crystal substrate on which the electrode is formed and a rear surface thereof opposed to the front surface.

Optical modulation device utilizing electro-optic effect

A scan chain circuit causes a plurality of flip-flops to function as shift registers during execution of a scan test and can execute a scan shift that serially transfers test pattern data for the scan test. A clock gating circuit controls output of a pulse of a clock signal supplied to the scan chain circuit in accordance with a clock gating signal, whereas disables the clock gating signal based on a logic of a scan enable signal authorizing the scan shift. A first clock gating circuit included in the clock gating circuit disables the clock gating signal during the scan shift based on the logic of the scan enable signal and also inverts the clock signal and outputs a result of inverting.

Semiconductor integrated circuit and design automation system

A semiconductor integrated circuit has a memory circuit having memory cells, a first register, a second register, a register selection circuit having an input to which an output of the first register and an output of the second register are connected, a memory bypass circuit which is located between a first switching circuit and a second switching circuit, and connected to the inputs and the outputs of the memory circuit. The register selection circuit is switched to the output signals of the first register when performing testing by way of the memory circuit, and switched to output signals of the second register when performing testing by way of the memory bypass circuit.

Semiconductor integrated circuit, design support software system, and automatic test pattern generation system

A semiconductor integrated circuit contains a logic circuit which operates upon receiving a clock; a logic built-in self test circuit which executes a built-in self test of said logic circuit, said logic built-in self test circuit having a pattern generator which generates a pattern to be input to said logic circuit, a pattern compactor which receives data output from said logic circuit that has received the pattern, compacts the data, and outputs a result, and a logic built-in self test control unit which controls operations of said pattern generator and said pattern compactor and controls an operation of causing a scan path in said logic circuit to shift upon receiving the pattern; a device circuit which operates upon receiving the clock; and a device circuit built-in self test circuit which executes a built-in self test of said device circuit.

Semiconductor integrated circuit having built-n self test circuit of logic circuit and embedded device, and design apparatus thereof

An optical device including (a) a substrate having an electro-optic effect; (b) a modulating optical waveguide formed on a surface layer portion of said substrate and forming an interference optical modulator for modulating input light; (c) an output optical waveguide formed on said surface layer portion of said substrate and connected to a downstream side portion of said modulating optical waveguide; and (d) a branching monitoring section for monitoring branched light of light propagated along said output optical waveguide and emitted from an outgoing end face of said substrate. The output waveguide has a reduced width region in which the waveguide width is reduced.

Optical device

The invention relates to an optical device which can increase the spread of a beam diameter in the depthwise direction by a simple configuration in comparison with that by prior art devices. The optical device includes a substrate, an optical path formed on the substrate, and a diffraction propagation region, provided between the optical path and an end face of the substrate, for propagating light emitted from the optical path with diffraction. The diffraction propagation region includes a first groove, formed therein, adapted to block part of components of the propagated light in a depthwise direction of the substrate.

Optical module and optical switching device

Optical waveguides (A) and (B) of a Mach-Zehnder modulator is normally formed on a &#x2212;Z plane as an electric polarization non-inversion area. However, when the signal electrodeand the ground electrodeare provided asymmetrically on two waveguides, chirp occurs in output light, which is undesired. Therefore, these electrodes are provided symmetrically about the two waveguides. To effectively perform optical modulation, a part of the substrate in which an optical waveguide exists is to be electric polarization-inverted. As a result of the electric polarization inversion the optical waveguide is on the +Z plane. However, electric charge is accumulated on the +Z plane from unstable spontaneous electric polarization of an electric polarization inversion area, and has undesired influence on the performance of the optical modulator. Therefore, a conductive amorphous layer is formed on the surface of the electric polarization inversion area.

Semiconductor integrated circuit, design support software system and automatic test pattern generation system

An optical device including (a) a substrate having an electro-optic effect; (b) an optical waveguide formed on a surface layer portion of said substrate and including an optical waveguide for performing optical modulation for light inputted to said substrate and an output optical waveguide and a monitoring optical waveguide branched from and connected to a downstream side portion of said modulating optical waveguide, said monitoring optical waveguide guiding light for monitoring optical modulation operation of said modulating optical waveguide; and (c) a reflecting portion being provided on the downstream side of said monitoring optical waveguide for reflecting light propagated along said monitoring optical waveguide, the width of a reflection face of said reflecting portion being substantially equal to the cut-out width of said monitoring optical waveguide.

An optical device is disclosed which suppresses a bias shift which is a deviation of a phase relationship between output signal light and monitoring light. The optical device includes a substrate having an electro-optic effect, a modulating optical waveguide formed on a surface layer portion of the substrate and forming an interference optical modulator for modulating input light, and an output optical waveguide and a monitoring optical waveguide each formed on the surface layer portion of the substrate and branched from and connected to a downstream side portion of the modulating optical waveguide. The monitoring optical waveguide guides light for monitoring optical modulation operation of the modulating optical waveguide. The monitoring optical waveguide has a reduced width region which has a reduced waveguide width.

A method for generating a test vector of an IC including: designating a retrieval condition to select a path on which a signal can be transmitted in the circuit; executing a timing analysis of the circuit based on a circuit information of the circuit, retrieving the path satisfying the retrieval condition, and generating a path list in which cells composing the retrieved path are put in order of executing the timing analysis; generating a test vector to test a path delay fault of the circuit based on the path list; designating an ending condition to end generation of the test vector when the path in the path list for the test vector is distributed over the circuit; and stopping generation of the path list when the ending condition is satisfied.

Apparatus for delay fault testing of integrated circuits

A semiconductor integrated circuit includes a self-testing circuit having a test circuit which is incorporated in a logic circuit to test the logic circuit. The test circuit has a test pattern generator to generate a test pattern and a compressor to compress a test result output. The logic circuit includes a plurality of scan chains including a plurality of serial connected registers and the compressor includes a through output portion. The semiconductor integrated circuit also includes a pattern counter which counts the test pattern at a test time of the logic circuit, a shift counter which counts the number of shifts in the scan chain in the logic circuit at the test time, and a failure information output circuit which is connected to the test circuit and which outputs step information of the test pattern corresponding to a failure to an integrated circuit external terminal when the failure is detected at the test time.

Growing community of inventors

Kawasaki, Japan

Tetsu Hasegawa