Nissan Motor Company Limited

Teruyoshi Mihara

Tsutomu Matsushita

Masakatsu Hoshi

Kenji Yao

Tamotsu Tominaga

Yukitsugu Hirota

Takeshi Oguro

Masami Takeuchi

Kraisorn Throngnumchai

Yoshinori Murakami

Tetsuya Hayashi

Hideaki Tanaka

Koichi Murakami

Masaki Hirota

Saichirou Kaneko

Toshiro Shinohara

Noriyuki Abe

Yoshio Shimoida

Norio Fujiki

Hiroshige Fukuhara

Hideo Muro

Norihiko Kiritani

Yukio Hiramoto

Yutaka Enokido

Kraisom Throngnumchai

The present invention-provides a tunnel-injection device which encompasses, a reception layer made of a first semiconductor, a barrier-forming layer made of a second semiconductor having a bandgap-narrower than the first semiconductor, being in metallurgical contact with the reception layer, a gate insulating film disposed on the barrier-forming layer. The gate electrode controls the width of the barrier generated at the heterojunction interface between the reception layer and the barrier-forming layer so as to change the tunneling probability of carriers through the barrier. The device further encompasses a carrier receiving region being contact with the reception layer and a carrier-supplying region being contact with the barrier-forming layer.

Insulated gate tunnel-injection device having heterojunction and method for manufacturing the same

A high reverse voltage diode includes a hetero junction made up from a silicon carbide base layer, which constitutes a first semiconductor base layer, and a polycrystalline silicon layer, which constitutes a second semiconductor layer, and whose band gap is different from that of the silicon carbide base layer. A low concentration N type polycrystalline silicon layer is deposited on a first main surface side of the silicon carbide base layer, and a metal electrode is formed on a second main surface side of the silicon carbide base layer which is opposite to the first main surface side thereof.

High reverse voltage silicon carbide diode and method of manufacturing the same high reverse voltage silicon carbide diode

A semiconductor structure having a plurality of drivers in and on the same semiconductor substrate is arranged to increase the density of integrated components and reduce the on resistance. The semiconductor structure employs a double layer interconnection structure having source and drain electrodes at two different levels, and an insulated gate electrode in a groove formed the semiconductor substrate. Each drain lead region having a low resistivity material extends from the upper surface of the substrate to a low resistivity buried layer. Each drain opening is surrounded by a source zone formed with a series of source holes or a long and narrow source slot, and this basic pattern is regularly repeated in a plane.

Groove-type semiconductor device

A semiconductor device having a surge input detecting circuit is provided with the driving circuit for, for example, reversible motor. To prevent MOS power transistors constituting the power driving circuit from their destructive breakdowns (failures), when the surge input detecting circuit block detects the surge voltage input through the driving circuit which exceeds a predetermined voltage, namely, a maximum rated power supply voltage of the power driving circuit, the surge input detecting circuit outputs the signal to turn the MOS power transistors in off-states. These circuit elements are integrally mounted on a semiconductor chip. The surge input detecting circuit block detects such a surge input through a power supply terminal in terms of either of its voltage, its current, or the temperature rise in the semiconductor chip. The breakdown voltage per power transistor can be half the maximum rated power supply voltage. In addition, the surge input detecting circuit block and these power MOS transistors are fabricated into the same semiconductor chip.

Motor driving circuit with surge detection/protection and its structure

A lateral double-diffused MOSFET has a semiconductor substrate, a drain region formed on the substrate, a gate insulation film formed on the drain region, a gate electrode formed on the gate insulation film, source and drain openings formed through the gate electrode, a first conductive region formed under the drain region, a source electrode formed on the source openings, a drain electrode formed on the drain openings, and second conductive regions for connecting the drain electrode to the first conductive region. The source and drain openings are cyclically arranged so that at least two rows of source openings are arranged between adjacent drain openings, to reduce the ON resistance of the MOSFET.

Lateral double-diffused mosfet

In a radar target position detecting apparatus, beams (, for example, light beams) irradiated from a transmitter(, for example, LED) have a predetermined divergence angle, a plurality of light (beam) receiving elements such as photodiode arrays each having a different receiving angle (directivity) are arranged in an array form, and a direction of a reflected wave (beam) is identified according to a position of the arrayed beam (wave) receiving elements in the array at which the reflected wave (beam) is captured.

Target position detecting apparatus and method utilizing radar

A transistor circuit such as an integrated circuit contains at least first and second MOS transistors having drain electrode pair and source electrode pair, one of which is a pair of electrodes connected together and integrated into a common drain or source electrode, and the other of which is a pair of separate electrodes. In a semiconductor substrate, there are formed at least one common region, such as a drain contact region or a source region, connected with the common electrode, and a plurality of first and second individual regions selectively connected with the separate electrodes. Around the common region or each common region, a predetermined number of the individual regions are arranged in such a manner as to improve the thermal balance of the substrate and enable the downsizing of the device.

MOSFET circuit with separate and common electrodes

In a semiconductor device having island regions formed in a surface area of a substrate, the island regions are electrically isolated from the substrate via buried regions formed of polycrystalline or amorphous semiconductor, without use of epitaxial growth technique. Since the polycrystalline or amorphous semiconductor includes a great number of recombination centers, parasitic operation between the elements formed on the semiconductor substrate can be prevented. Further, the buries regions are excellent in heat conductivity, the breakdown resistance against surge voltages or static electricity can be improved. Furthermore, when applied to a CMOS, it is possible to prevent latch up action caused by a parasitic thyristor formed in the CMOS, by the presence of the buried regions including a great number of recombination centers.

Method for forming PN junction isolation regions by forming buried

A lateral DMOS FET device which has a small on resistance. The device includes a cell structure formed by a plurality of unit cells, each unit cell including: a source region of first conduction type formed on one side of a substrate of first conduction type; a channel region of second conduction type formed around the source region; and a plurality of drain contact regions of first conduction type located around the channel region; and a source electrode, a gate electrode, and a drain electrode, all of which are formed on the same one side of the substrate. Alternatively, each unit cell may includes: a drain contact region of first conduction type formed on one side of a substrate of first conduction type; a channel region of second conduction type formed around the drain contact region; and a plurality of source regions of first conduction type located around the channel region.

Lateral DMOS FET device with reduced on resistance

A semiconductor device in which the breakdown voltages of the cell unit and the guard ring can easily be matched, and the surge endurance of the device can be improved. This semiconductor device includes a guard ring region surrounding the cell diffusion layers which is formed from an array of a plurality of guard ring cells, where each of the guard ring cells is identical to each of the cell diffusion layers and the guard ring cells are electrically connected mutually, so that the diffusion depths of each of the cells of the guard ring region and the cell diffusion layers are identical, and consequently the breakdown voltages for the guard ring region and the cell diffusion layers can be made equal to each other.

Semiconductor device with high surge endurance

A method of manufacturing semiconductor devices by forming a U-shaped insulated gate on a substrate, etching the substrate to expose a sidewall of the U-shaped insulated gate, covering the exposed part with a masking material, forming the sidewall of the masking material only adjoining to the exposed U-shaped insulated gate, etching the substrate vertically to form a groove, forming a semiconductor region on the groove and burying a metal into the groove.

Method of manufacturing semiconductor device utilizing an accumulation

A semiconductor device includes a semiconductor substrate of a first conductivity type, in which a drain region is formed in the substrate, and a gate electrode is formed on the surface of the substrate via an insulating film formed thereon. A Schottky metal as a source region is formed in the surface of the substrate away from the drain region, the Schottky metal and the substrate constituting a Schottky junction at an interface therebetween near the gate electrode. A shield layer of a second conductivity type is interposed between the Schottky metal and the substrate except in the Schottky junction. The gate electrode controls tunnel current at the Schottky junction.

Schottky tunnel transistor device

A semiconductor device includes a semiconductor substrate as a drain region. A metal source region is located on a first surface of the substrate. The metal and the substrate constitute a Schottky junction. An insulated gate, including a gate electrode and an insulating film surrounding the gate electrode, is adjacent to the Schottky junction, such that angle formed by the Schottky junction and the insulated gate in the substrate is an acute angle. A part of the Schottky metal can be buried in the form of a pillar in the substrate, and a channel region of the Schottky junction can be formed on the pillar near the insulated gate.

Semiconductor device

A MOSFET device including a power MOSFET and a current mirror MOSFET, in which the drains of the two MOSFETs are coupled in common to each other, and the gate electrodes of the two MOSFETs are linked in common to each other, and in which a diode device for protecting a gate oxide film for the current mirror MOSFET is connected between the sources of the two MOSFETs.

MOSFET including current mirror FET therein

A conductivity modulated MOSFET is composed of a p.sup.+ anode layer, a second n base layer formed on the anode layer for reducing the device's on resistance by conductivity modulation due to holes injected from the anode layer, an n type doped recombination layer such as an n type doped polycrystalline silicon layer formed on the second base layer for preventing latch-up by promoting recombination of holes with electrons, a first n base layer formed on the recombination layer for serving virtually as a drain, a p channel region formed in the first base layer, an n.sup.+ source region formed in the channel region, and an insulated gate electrode.

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Yokosuka, Japan

Teruyoshi Mihara