Hitachi, Ltd.

Nisshin Steel Co., Ltd.

Hitachi Vlsi Engineering Corp.

Bridgestone Corporation

Hitachi Ulsi Engineering Corp.

Teruo Tanaka

Naoki Hamanaka

Shigeo Nagashima

Yasuhiro Inagami

Yoshiko Tamaki

Tadayuki Sakakibara

Katsuyoshi Kitai

Koichiro Omoda

Junji Nakagoshi

Tadaaki Isobe

Shigeo Takeuchi

Akira Muramatsu

Kazuo Nakao

Ikuo Yoshihara

Takehisa Hayashi

Takayuki Nakagawa

Katsuhisa Miyakusu

Hiroshi Fujimoto

Yoshiko Yasuda

Makoto Nohmi

Tatsuo Higuchi

Kazuo Hoshino

Takashi Igawa

Kousuke Sakoda

Masayuki Kinugasa

Toshihiko Takemoto

Yasuhiro Ogata

Taturu Toba

Shinichi Shutoh

Shigeko Hashimoto

Takahiro Nakano

Masaaki Iwasaki

Tadashi Takeuchi

Naoko Ikegaya

Hiroaki Fujii

Sigeo Ihara

Kazuo Ojima

Mamoru Sugie

Taketoshi Sakuraba

Kyoko Iwasawa

Hiroyuki Chiba

Hideo Wada

Yuji Saeki

Tatsuru Toba

Toshiro Yamada

Shigeko Yazawa

Masanao Ito

Hiromitsu Maeda

Mitsuyoshi Igai

Tsunetoshi Suzaki

Tomoyoshi Iwao

Kenjiro Ito

Yukio Saegusa

Koichiro Omada

Chizui Toyokihara

Naoko Hamanaka

Tadayuki Sakakibaraa

Keiichi Tachibana

In order to manufacture a radial tire, first, in an average waveform recording step, a waveform component of radial force variation (RFV) by a molding factor in each molding machine, and a waveform component of RFV by a vulcanization factor in each vulcanizer are respectively acquired and recorded in a computer. In a waveform synthesizing step, a radial run-out (RRO, that is, vibrations resulting from non-uniformity of a tire surface) waveform of a green tire is substituted by an RFV waveform component and is made to overlap with respective RFV waveform components of waveforms of a molding factor and a vulcanization factor, thereby obtaining an RFV composite waveform. In a selection step, a circumferential position on the green tire at which an amplitude of the RFV composite waveform becomes minimum, and the circumferential position in a vulcanization mold are selected. Further, in a vulcanization step, based on the selected circumferential positions, the green tire is disposed and vulcanized in the vulcanization mold. As a result, a radial tire of which RFV is sufficiently reduced can be obtained.

Radial tire manufacturing method

A computer connected to a plurality of computers, having: a storage area for storing data representative of properties of the plurality of computers relative to the computer; a data area for storing data to be used by the plurality of computers; and a program for determining a computer which holds data in the data area in accordance with a request for the data area. The computer can recover data lost from the computer from a proper area. Each of the properties of the plurality of computers is represented by a value determined by at least one of a computer fault occurrence frequency, a data transfer speed relative to the computer, an importance degree of data shared by processing programs of the plurality of computers. In accordance with the value in the storage area, the data in the data area,can be stored in multiples or in divisions.

Data transfer control method and system, data transfer control program file, and file storage medium

Before starting data transfer, the sender node sends the CONNECT message requesting security of hardware resources necessary for data transfer to the receiver node. Each node relaying the CONNECT message secures the CPU time and bandwidth necessary for data transfer and sends the CONNECT message to the receiver node. Upon receipt of the CONNECT message, the receiver node reserves the CPU time necessary for data reception and then sends the ACCEPT command to the sender node. The sender node receives the ACCEPT command and then sends a data packet.

Media data communication method via network

Computer system

A parallel computer using a simply structured network which allows loads on message-transferring routes to be as equally distributed as possible and which eases possible conflict between different types of messages being transferred. Given a message to be transmitted, each processor (PE) on the network references a property setup table to determine property information depending on the message type and places the information into the message. For example, a route bit RB as the property information is set to '0' or '1' depending on whether the message is originated by the sending PE or is a message acknowledging the receipt of another message. According to the RB bit in the received message, a route instruction circuit in each exchange switch (EX) references a route instruction table to determine the message destination that depends on the receiving PE number designated by the message. Each EX has a plurality of virtual channel circuits. Each virtual channel circuit has a plurality of buffers assigned beforehand to different values of the RB bit within the message. The received message is placed into the buffer corresponding to the RB bit value of the message, whereby conflict between messages is minimized.

Parallel computer system using properties of messages to route them

In a multiprocessor computer system, individual vector processors are provided with priority switching signal control circuits, respectively, and a storage control unit incorporating a priority control circuit. Priority bit information is provided for priority circuits incorporated in the storage control unit. Paths for priority switching signal issued in accordance with a number of requests as generated and types of instruction generating the requests are provided between the priority switching signal control circuits and the priority control circuit of the storage control unit, while paths for the priority switching signal as generated are provided between the priority control circuit and all the priority circuits.

Priority control with concurrent switching of priorities of vector

In order to determine a transfer path of a message to a receiving-end processor group, a processor includes a routing bit generation circuit, and an exchange switch includes partial broadcast path control circuits and a path control information alteration circuit. In order to define the range of a receiving-end processor group, a network includes transfer control circuits. A crossbar switch includes transfer control circuits associated with output ports and a boundary register group. When a partial broadcast message is transferred from an input port in the downstream direction of an output port, it is decided whether a belonging to the partial broadcast range associated with a connected to the particular input port is connected to the particular output port, whereby the particular partial broadcast message is transferred from the same output port.

Partial broadcast method in parallel computer and a parallel computer

In a parallel processor system comprising a plurality of processor elements constituting a network, a source processor element wishing to broadcast data to a plurality of destination processor elements sends a broadcast request message containing the target data to a broadcast exchanger. The broadcast exchanger converts the received message into a broadcast message and sends it over the network to the destinations. A plurality of broadcast request messages, if transmitted parallelly to the broadcast exchanger, are serialized thereby so that only one broadcast message will be transmitted at a time over the network. This prevents deadlock from occurring between different broadcast messages. The routes for transmitting broadcast request messages and those for transmitting broadcast messages are arranged so as not to overlap with one another. This suppresses deadlock between any broadcast request message and broadcast message. The broadcast exchanger is replaced alternatively with one of the partial networks. These schemes all apply where long messages are transmitted through worm-hole routing.

Parallel processor system with a broadcast message serializing circuit

In order to make use of row address lock mode of operation of a plurality of memory banks comprising synchronous DRAMs or the like and divided into a plurality of real bank groups, for example, for example, more than the memory banks are grouped into a plurality of logical groups each spanning the real bank groups. Addresses are allocated in unit of each logical group in a block-interleaving manner. When a series of requests issued by a given requester include a plurality of requests for accessing the same row address in the same memory bank, that requester requests that the row address be locked for access by the plurality of requests. The lock request is retained by a row address management unit. When a succeeding request from another requester requests access to a row address other than the locked address in the same memory bank, a priority circuit selects a predetermined number of requests from the initial requester having locked the memory in preference to a request made by the other requester.

Processor system having address allocation and address lock capability

Preload register groups are respectively provided for the plurality of scalar processors which execute iterative processing in distributed manner. Each group consists of preload registers corresponding to a plurality of data arrays that appear in the iterative processing. According to address information about the plurality of arrays to be preloaded specified by any of the processors, a preload control unit reads partial data groups of one of the arrays to be first processed by all of the processors from the main storage in parallel. Then, the same operation is performed on another array. Subsequently, in the above-mentioned manner, remaining elements of the arrays are read from one array to another. A partial element group thus read sequentially is stored in the plurality of preload register groups in distributed manner. According to a load request issued from each processor, the array elements preloaded in the preload register groups corresponding to that processor are read in the order the array elements were preloaded.

Data processor system for preloading/poststoring data arrays processed

A parallel processor system including a plurality of processors. When packets of same destination PE number are inputted from different ports, the destination PE number is added with ID numbers of leading ports of split crossbar switches to which the different input ports belong, respectively, by using respective addition circuits, to thereby determine a transfer destination output port for the packets. A plurality of the split crossbar switches having different numbers of input/output ports are realized by partitioning a crossbar switch. By means of an input port select circuit provided in association with each of the output ports, an output request for the packet from the input port belonging to the split crossbar switch to which the associated output port belongs is accepted, while output requests for the packets from the input ports belonging to the other split crossbar switches are inhibited from being accepted, whereby transfer of broadcast packets are inhibited between the split crossbar switches belonging to a physically same crossbar switch. Such situation can be evaded in which same broadcast packets arrive at one and the same processor a number of times.

Switch circuit comprised of logically split switches for parallel

An operation complete signal and a convergence result signal from each processor are transferred to the X-direction interconnection switches, AND of these signals is obtained in switch units in each interconnection switch, the signal is sent out to all the Y-direction interconnection switches through a synchronizing signal relay switch and the like in each relay switch, AND of these signals is obtained in each switch unit in the interconnection switches, and the result thereof is transferred to each processor through each synchronizing signal relay switch. With this, a logical product of an operation complete signal and a logical product of a convergence result signal from all the processors are sent in parallel to all the processors.

Parallel computing system for synchronizing processors by using partial

A parallel computer includes a plurality of processor elements (1-1 to 1-n) connected by a network (2); each processor element includes a local memory (6) for holding a program and related data, a processor (3) for performing an instruction in said program, a circuit (5) for transferring data to other processor elements, and a circuit (4) for receiving data sent from another processor element; a memory area (92,8) includes of a plurality of reception data areas for temporarily storing data received by said receiving circuit, and memory (92,8) constructed of a plurality of tag areas, provided for each reception data area, for storing a data tag indicating validity of data in the corresponding reception data area; a transmitting circuit (5) for transmitting data with an attached data identifier predetermined by said data; a circuit for writing the data into one of the plurality of reception data areas in response to data received from the network, and writing valid data tag into one of said plurality of reception data areas, the receiving circuit being parallelly-operated with the processor; and, an access circuit (38) for reading both data and tag from one of the reception data areas determined by the data identifier and from the corresponding tag areas, in response to a data identifier designated by the instruction which is produced from said program for requiring data reception, and for repeatedly reading a tag and data from the tag reception data areas until a valid data tag is read therefrom.

Parallel computer comprised of processor elements having a local memory

Interprocessor priority control system for multivector processor

A vector processor includes a storage control apparatus which incorporates an access request buffer unit equipped with an address decoding unit having address decoder circuits corresponding to all models of the vector processors belonging to a same machine series. By using model ID signals, the address decoding is selectively enabled by a selector. The address decoding unit equalizes the periodicities at which the address assignments to the memory modules are skewed or shifted for all the element parallelism factors of the processors belonging to the same machine series. Access request queue is provided in a necessary number of stages in precedence to an access request priority determining unit incorporated in the storage control apparatus.

Vector processor adopting a memory skewing scheme for preventing

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Hachioji, Japan

Teruo Tanaka