Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Kioxia Corporation

Teruo Takagiwa

Masatsugu Ogawa

Masami Masuda

Hitoshi Shiga

Masahiro Yoshihara

Koichi Fukuda

Katsumi Abe

Osamu Nagao

Ayako Yamano

According to one embodiment, a semiconductor memory device includes a first string including a first memory cell transistor and a second memory cell transistor which are coupled in series, a first switch element, a first latch circuit coupled in series between a first end of the first string and a first end of the first switch element, and a second switch element and a third switch element coupled in parallel between a second end of the first switch element and a data bus.

Semiconductor memory device

A memory system includes a semiconductor memory and a memory controller. The semiconductor memory includes first memory cells, first bit lines connected to the first memory cells, second memory cells, second bit lines connected to the second memory cells, a word line connected to the first and second memory cells, and a driver configured to apply a voltage to the word line. In response to a special read command from the memory controller, the driver sequentially applies, to the word line, first read voltages to read data from the first memory cells, a second read voltage within a voltage range of the first read voltages to read data from the first memory cells, third read voltages to read data from the second memory cells, and a fourth read voltage within a voltage range of the third read voltages to read data from the second memory cells.

Memory system

According to one embodiment, a semiconductor storage device is disclosed. The device includes a memory cell array including memory cells, bit lines connected to the memory cell array, sense amplifier units provided to correspond to bit lines and arranged in a matrix of M rows and N columns, data latches provided to correspond to sense amplifier units and arranged in a matrix of S rows and T columns. M, N, S, and T are positive integers, satisfying M&#x3c;S, N&#x3e;T, and S&#xd7;T=M&#xd7;N. A dimension of each of the sense amplifier units in an arrangement direction of the N columns is smaller than a dimension of each of the data latches in an arrangement direction of the T columns.

Semiconductor storage device

According to an embodiment, a semiconductor memory device includes a first memory cell, a first interconnect, a first sense amplifier, a second interconnect, and a first latch circuit. The first interconnect is coupled to the first memory cell and extends in a first direction in a first interconnect layer. The first sense amplifier is coupled to the first interconnect. The second interconnect is coupled to the first sense amplifier and extends in the first direction in the first interconnect layer. The first latch circuit is coupled to the second interconnect. An end surface of the first interconnect on a side facing the first direction is opposed to an end surface of the second interconnect on a side facing a direction opposite to the first direction.

A data latch circuit includes a first inverter circuit having a first input terminal and a first output terminal, and connected between a first voltage source and a second voltage source, a second inverter circuit having a second input terminal electrically connected to the first output terminal and a second output terminal electrically connected to the first input terminal, and connected between the first voltage source and the second voltage source, a first transistor electrically connected between the first voltage source and the first inverter circuit, a second transistor electrically connected between the second voltage source and the first inverter circuit, a first switch circuit that controls an electrical connection between the first output terminal and a first bus, and a second switch circuit that controls an electrical connection between the first output terminal and a second bus.

Data latch circuit

A semiconductor memory device includes a plurality of memory cells, a data bus connected to a first column of the memory cells, by which data is transferred to and from the memory cells of the first column, a data latch storing data indicating whether the first column is defective or not, and a transistor having a first terminal connected to the data bus, a second terminal connected to a voltage source, and a gate connected to an output of the data latch.

According to one embodiment, a semiconductor memory device includes: a memory cell array; a first data latch; a second data latch; a first data bus; a second data bus; a first temporary latch; a second temporary latch; and a control unit. The first and the second data latches are electrically connected to the memory cell array. The first data bus is electrically connected to the first data latch. The second data bus is electrically connected to the second data latch. The first temporary latch is electrically connected to the first data bus. The second temporary latch is electrically connected to the second data bus. The control unit is configured to write data on the first temporary latch and transfer data retained in the first temporary latch to the first data latch while writing data on the second temporary latch.

According to one embodiment, a semiconductor memory device includes a plurality of blocks in a memory cell, each of the blocks acting as an erasure unit of data, the block including a plurality of pages, each of the pages including a plurality of memory cell transistors, each of the memory cell transistors being configured to be an erasure state or a first retention state based on a threshold voltage of the memory cell transistor, and a controller searching data in the block with respect to, writing a first flag denoting effective into a prescribed page of the block with the erasure state, and writing the first flag denoting non-effective into a prescribed page of the block with the first retention state, reading out the prescribed page of the block with the first retention state, and determining that the block is writable when the first flag denotes effective.

Semiconductor memory device and method for writing therein

According to one embodiment, a semiconductor memory device includes n (n being a natural number of 2 or more) data retention circuits connected to a data input/output terminal; n buses connected respectively to the n data retention circuits; m&#xd7;n data latch circuits connected to the buses, with m (m being a natural number of 2 or more) data latch circuits being connected per one of the buses; and a selection circuit configured to simultaneously perform data transfer from/to the data retention circuits for a plurality of the data latch circuits in units of a group including the plurality of the data latch circuits, the data latch circuits being divided into the groups so that not all the data latch circuits connected to the same bus are included in the same group.

A semiconductor memory device according to an embodiment includes a memory cell array that includes a plurality of cell columns each configured by a plurality of memory cells, and a column control circuit that includes a plurality of sense amplifier-data latch units each including a plurality of sense amplifiers that detect and amplify data of the memory cells and a plurality of data latches. One of the plurality of sense amplifier-data latch units is a first sense amplifier-data latch unit and another of the plurality of sense amplifier-data latch units is a second sense amplifier-data latch unit, the first sense amplifier-data latch unit and the second sense amplifier-data latch unit having different numbers of the cell columns capable of being handled.

According to one embodiment, a memory includes main and redundancy regions including cells, first units in the main region, second units in the redundancy region, a column control circuit configured to selects the first units using a first pointer corresponding to an address signal, and selects the second unit using a second pointer when defect address of the main region matches the address signal so that defect first unit is replaced with the second unit, a selection circuit configured to connects one of a first path for the main region and a second path for the redundancy region to a third path based on a comparison result between the address signal and the defect address.

Semiconductor memory and method of controlling the same

According to one embodiment, a nonvolatile semiconductor memory includes memory cells arranged in a memory cell array in the form of a matrix, the memory cell storing data having two or more levels associated with two or more threshold levels, respectively, a buffer circuit including latch circuits and sense amplifier circuits, each latch circuit and each sense amplifier being associated with each column in the memory cell array, and a control circuit configured to control operations of the memory cells and the buffer circuit, the control circuit executing data writing with respect to the memory cells and first verification using judgment information indicative of a result of the data writing in a write sequence with respect to data from the outside. The judgment information is assigned to two or more threshold levels, which are not adjacent to each other, in common.

Nonvolatile semiconductor memory and method of operating the same

According to one embodiment, a semiconductor memory device includes a plurality of memory cells, and a plurality of latch circuits. The memory cells are associated with columns and are capable of storing data. The latch circuits are associated with the columns and are capable of storing write data and/or read data for the columns. The latch circuits are selectively activated, and activated latch circuits are capable of receiving and/or outputting data.

Semiconductor memory device and method for controlling the same

According to one embodiment, a semiconductor memory device includes memory cells, holding circuits, and a logical gate chain. The memory cells are associated with columns. The holding circuits are associated with the columns and capable of holding first information indicating whether associated one of the columns is a verify-failed column or not. The logical gate chain includes a plurality of first logical gates associated with the columns and connected in series. Each of the first logical gates outputs a logical level to a next-stage first logical gate in a series connection. The logical level indicates whether the verify-failed column exists or not based on the first information in associated one of the holding circuit. The content indicated by the logical level output from each of the first logical gates is inverted using one of the first logical gates associated with the verify-failed column as a border.

Growing community of inventors

Yokohama, Japan

Teruo Takagiwa