Sanyo Electric Co., Ltd.

Teruo Tabata

Nobuyuki Sekikawa

Tadayoshi Takada

Yoshiaki Sano

Toshimasa Sadakata

Chikao Fujinuma

Kazuo Takeda

Yasuhiro Tamada

A method of making a semiconductor integrated circuit provided with an isolating region constituted of an upper and lower isolating regions, and integrated circuit element regions is disclosed, wherein: the lower isolating region is diffused upward to a depth of a little more than half the thickness of an epitaxial layer to link with the upper isolating region prior to a doping of the upper isolating region; the doping of the lower isolating region and integrated circuit element regions, is implemented by means of ion implantation through a resist film which is capable of blocking ions implanted and in which specified doping windows have been formed in advance, and a SiO.sub.2 film is used as a reference mask in an ion implanting step, and the respective borders of the upper isolating region and the specified regions of the circuit elements is determined by self-alignment. The method has advantages that the upper isolating region can be prepared by heat-treatment for relatively short time, reducing lateral diffusion and the occupied area thereof, and slippage by masking is remarkably reduced, providing a semiconductor integrated circuit with high density.

Method for manufacturing a semiconductor integrated circuit

A method of manufacturing a semiconductor integrated circuit comprises the steps of: forming an epitaxial layer covering a semiconductor substrate and buried layers; forming isolation regions dividing the epitaxial layer into a plurality of islands; forming a lower electrode region of an MIS type capacitor in one of the islands; forming a base region of a vertical bipolar transistor simultaneously with or independently from the lower electrode in another island; depositing a thin dielectric layer of the MIS type capacitor on a portion of the lower electrode region; thereafter selectively diffusing impurities into the surface layer of the base region so as to form an emitter region of the vertical bipolar transistor; and forming an upper electrode of the MIS type capacitor on the thin dielectric layer.

Semiconductor integrated circuit and manufacturing method therefor

The present invention relates to a semiconductor device and a method of producing the same. According to this method, a lower diffusion layer of a double isolation diffusion area is attached to a surface of a substrate, an epitaxial layer being formed on the lower diffusion layer, the lower diffusion layer being largely outdiffused upwardly in the epitaxial layer and simultaneously an element diffusion area being deeply diffused from a surface of the epitaxial layer, and then an upper diffusion layer of the double isolation diffusion area being shallowly diffused from the surface of the epitaxial layer. Thus, the lateral expansion of the upper diffusion layer of the double isolation diffusion area can be suppressed and the integrated extent can be improved. On the other hand, in a semiconductor device of the present invention, the above described double isolation diffusion area is formed and a collector area, a base area and an emitter area are formed all over the width of the epitaxial layer (the base area and the emitter area are formed by a double diffusion). In addition, it includes a vertical type transistor whose fluctuation of a width of the base area is reduced, so that the transition frequency f.sub.T and current gain h.sub.FE of this transistor are increased.

Method of making a bipolar transistor with double diffused isolation

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Gunma, Japan

Teruo Tabata