Renesas Technology Corp.

Teruo Shoji

Akio Hasebe

Yasunori Narizuka

Susumu Kasukabe

Yasuhiro Motoyama

Yoshinori Deguchi

Akira Yabushita

Yuji Wada

Terutaka Mori

Takehiko Hasebe

Masakazu Sueyoshi

Masayoshi Okamoto

Motoji Murakami

By using a membrane probe formed by using a manufacturing technique for semiconductor integrated circuit devices, the yield of probing collectively performed on a plurality of chips is to be enhanced. A probe card is formed by using a plurality of pushers, each pusher being formed of a POGO pin insulator, POGO pins, an FPC connector, a membrane probe HMS, an impact easing sheet, an impact easing plate, a chip condenser YRS and so on, wherein one or two POGO pins press a plurality of metal films arranged like islands. One or more cuts are made into what matches the chip to be tested in the area of the membrane probe in a direction substantially parallel to the extending direction of wiring electrically connected to probes formed in the membrane probe.

Manufacturing method of semiconductor integrated circuit device

In a prove card comprising: a probe sheet having a contact terminal contacting with an electrode provided on a wafer, a wiring led from the contact terminal, and an electrode electrically connected to the wiring; and a multilayered wiring substrate having an electrode electrically connected to the electrode of the probe sheet, wherein a contact between the contact terminal and the electrode of the wafer is established by one or more adhesion holder for pressing, from the backside of a terminal group of the terminal contacts, the terminal group via a press block with a spring to contact with the electrode pad. A device in which the probe sheet is attached to the adhesion holder and a plurality of chips are tested simultaneously by combining the adhesion holder.

Probe sheet adhesion holder, probe card, semiconductor test device, and manufacturing method of semiconductor device

The fabrication of a semiconductor integrated circuit device involves testing using a pushing mechanism that is constructed by forming, over the upper surface of a thin film probe, a reinforcing material having a linear expansion coefficient (thermal expansion coefficient) almost equal to that of a wafer to be tested; forming a groove in the reinforcing material above a contact terminal; placing an elastomer in the groove so that a predetermined amount projects out of the groove; and disposing a pusher and another elastomer to sandwich the pusher between the elastomers. With the use of such a probe, it is possible to improve the throughput of wafer-level electrical testing of a semiconductor integrated circuit.

Fabrication method of semiconductor integrated circuit device

Any damage inflicted on test pads, inter-layer insulating films, semiconductor elements or wiring at the time of electrical inspection of semiconductor integrated circuit devices is to be reduced. Reinforcements having a substantially equal linear expansion ratio (coefficient of thermal expansion) relative to a wafer to be inspected are formed over an upper face of a thin film probe, grooves are cut in the reinforcements above the probes, a first elastomer which is softer than a second elastomer is so arranged as to fill the grooves and overflow the grooves by a prescribed quantity, a glass epoxy substrate, which is a multi-layered wiring board, is fitted over the second elastomer, and pads provided over an upper face of the glass epoxy substrate and bonding pads which are part of wirings belonging to the thin film probe are electrically connected by wires.

Growing community of inventors

Mitaka, Japan

Teruo Shoji