Panasonic Corporation

Matsushita Electric Industrial Co., Ltd.

Teruo Kawabata

Taketo Heishi

Hajime Ogawa

Shohei Michimoto

Yasuhiro Yamamoto

Hirotetsu Tomita

Ryoko Miyachi

Tomoo Hamada

Kiyoshi Nakashima

Masatsugu Daimon

Kyoko Hattori

Kenji Hattori

A compiler apparatus, which can perform software pipelining optimization that has a considerable effect of reducing the number of execution cycles taken to complete a loop process, converts a source program into a machine program for a processor which is capable of parallel processing. The compiler apparatus is composed of: a parsing unit operable to parse the source program and then to convert the source program into an intermediate program which is described in an intermediate language; an optimization unit operable to optimize the intermediate program; and a conversion unit operable to convert the optimized intermediate program into the machine language program, wherein the optimization unit is operable to execute software pipelining, by inserting a transfer instruction, which is used for transferring data between operands, into a loop process included in the intermediate program so that a data dependence relation is changed.

Compiler apparatus

A compiler, which corresponds to a recent processor having a multithread function, that enables execution of efficient instruction scheduling and allows a programmer to control the instruction scheduling includes: an instruction scheduling directive receiving unit which receives, from a programmer, a directive for specifying an instruction scheduling method; and an instruction scheduling unit which executes, conforming to one of instruction scheduling methods, instruction scheduling of rearranging intermediate codes corresponding to the source program. The instruction scheduling unit selects one of instruction scheduling methods according to the directive received by the instruction scheduling directive receiving unit, and executes instruction scheduling conforming to the selected instruction scheduling method.

Program converting apparatus and program conversion method

A program re-writing method which re-writes an inputted program into a program for a processor for controlling whether or not a process is executed based on a yes or no execution flag, said program re-writing method including: inserting a comparison process into the inputted program, the comparison process comparing first address information, which is memory address information accessed by a first memory access process included in the inputted program, and second address information, which is address information of a memory accessed by a second memory access process included in the inputted program, and writing a comparison result into the yes or no execution flag; and inserting a yes or no execution flag-attached logic preservation process into the inputted program, the yes or no execution flag-attached logic preservation process being a process executed based on a value of the yes or no execution flag and preserving the same result as a result of the inputted program when executed.

Program re-writing apparatus

A compiler, which is a compiler that realizes program development in a fewer man hours, translates a source programwritten in a high-level language into a machine language program. This compileris comprised of: a directive obtainment unit that obtains a directive that a machine language program to be generated should be optimized; a parser unitthat parses the source program; an intermediate code conversion unitthat converts the source programinto intermediate codes based on a result of the parsing performed by the parser unit; an optimization unitthat optimizes the intermediate codes according to the directive; and a code generation unitthat converts the intermediate codes into the machine language program. The above directive is a directive to optimize the machine language program targeted at a processor that uses a cache memory.

Compiler apparatus for optimizing high-level language programs using directives

A compiler apparatus enables description of a particular hardware module in the existing programming language, although the description has not been possible in hardware designing to input programming language. In the header file, a particular hardware indescribable in programming language is defined. And the compiler apparatus includes a parser unitanalyzing syntax of source program, an intermediate code converting unitconverting the syntactically analyzed source programto an intermediate code and code generating unitconverting the intermediate code to the RTL description. The intermediate code converting unitincludes a detecting unitdetecting a particular hardware defined in the header fileout of the source programand a replacing unitreplacing the detected particular hardware in the detecting unitwith the intermediate code corresponding to a particular hardware.

Growing community of inventors

Osaka, Japan

Teruo Kawabata