Nippon Telegraph and Telephone Corporation

Teruo Jo

Hideyuki Nosaka

Munehiko Nagatani

Hiroshi Hamada

Hiroshi Yamazaki

Hiroyuki Fukuyama

Shinsuke Nakano

An embodiment includes an output circuit with transistors and a withstand voltage protection circuit. The withstand voltage protection circuit includes resistors connected between an output signal terminal on the positive phase side and an output signal terminal on the negative phase side. A switch includes an NMOS transistor having a gate terminal connected to the connection point of the resistors, a drain terminal connected to the bias voltage, and a source terminal connected to the base terminal of the transistor.

Driver circuit

The driver circuit includes DC cut capacitors, an input buffer, input termination resistors connected in series between differential input signal terminals and an ESD protection circuit connected to a connection point of the input terminal resistors. The ESD protection circuit includes diodes.

A distributed amplifier includes: a transmission line having an input end that an input signal is input to; a transmission line having an output end that an output signal is output from; an input termination resistor connected to an end terminal of the transmission line; a plurality of unit cells arranged along the transmission lines, and having input terminals connected to the transmission line and output terminals connected to the transmission line; and a variable current source having one end connected to the end terminal of the transmission line and another end connected to a power supply voltage, and capable of adjusting a current amount between the transmission line and the power supply voltage.

Distributed circuit

A voltage setting circuit includes a frequency comparator that compares the oscillation frequencies of a first distributed voltage-controlled oscillator and a second distributed voltage-controlled oscillator and a frequency determination circuit that determines the levels of the oscillation frequencies of the first distributed voltage-controlled oscillator and the second distributed voltage-controlled oscillator. The bias to be supplied to the first distributed voltage-controlled oscillator and the bias to be supplied to the second distributed voltage-controlled oscillator are determined in accordance with a result of the determination. The bias at a time when the levels of the oscillation frequencies are reversed is determined to be the optimum bias, and the optimum bias is supplied to the core circuit.

Voltage setting circuit, semiconductor integrated circuit and voltage setting method

An amplifier circuit comprises a variable degeneration circuit connected to emitter terminals of transistors, and a variable negative capacitance circuit connected to differential output signal terminals. The variable degeneration circuit includes a variable capacitor and a resistor. The variable negative capacitance circuit, which is a variable current source, includes a transistor, a capacitor, and a variable current source. The variable negative capacitance circuit includes transistors, a capacitor, and variable current sources.

Amplifier and driver circuit

A driver circuit includes a differential pair of transistors that amplify differential input signals and output the amplified differential input signals from signal output terminals, a current source that supplies a constant current to the differential pair of transistors, a switch that stops the current supply from the current source to the differential pair of transistors during a shutdown mode period, capacitors each having one end connected to the ground, a switch that connects the capacitor to the signal output terminal during the shutdown mode period and disconnects the capacitor from the signal output terminal during an amplification mode period, and a switch that connects the capacitor to the signal output terminal during the shutdown mode period and disconnects the capacitor from the signal output terminal during the amplification mode period.

A permittivity measuring method includes measuring a set of phases at sampling frequencies of at least three points in each of a first-half portion and a second-half portion of a phase characteristic of electromagnetic waves that passed through a measurement target, if the mode of the phase changes of both sets of phases belongs to a phase group in which change of the at least three points in the first half and change of at least three points in the second half are both monotonic change, maximal values, or minimal values, calculating the permittivity using the phase slope of the phases in the first-half portion and the phases in the second-half portion, and if the mode of the phase changes does not belong to the phase group, calculating the permittivity by fitting the phases of either the first half or the second half to a quadratic function.

Dielectric constant measurement method, dielectric measurement device and dielectric measurement program

An embodiment is a multiplexer including a first distributed amplifier with an impedance matched to 50Ω, the first distributed amplifier configured to receive a first signal and output a first amplified signal, a second distributed amplifier with an impedance matched to 50Ω, the second distributed amplifier configured to receive a second signal and output a second amplified signal, and a passive multiplexer configured to multiplex the first amplified signal and the second amplified signal, and output a multiplexed signal to a signal output terminal, the passive multiplexer including a first resistor having a first end to receive the first amplified signal, a second resistor having a first end to receive the second amplified signal, and a third resistor having a first end connected to second ends of the first and second resistors and a second end connected to the signal output terminal.

Multiplexer

An analog demultiplexer circuit includes a clock distribution circuit that outputs clock signals (CKP and CKN) and clock signals (CKP and CKN) complementary thereto, a track-and-hold circuit that holds analog input signals (VINP and VINN) in synchronization with the clock signals (CKP and CKN), and a track-and-hold circuit that holds the analog input signals (VINP and VINN) in synchronization with the clock signals (CKP and CKN).

Analog multiplexer circuit and analog-digital conversion system

In an embodiment, an edge extraction method includes: emitting, toward an object, an electromagnetic wave polarized only in one direction perpendicular to a propagation direction; receiving a transmitted electromagnetic wave that has been transmitted through the object, using a receiving antenna; calculating an intensity in the propagation direction of the transmitted electromagnetic wave based on an intensity of the transmitted electromagnetic wave received by the receiving antenna; and obtaining a spatial distribution of the intensity in the propagation direction of the transmitted electromagnetic wave.

Edge extraction method and edge extraction device

A distributed amplifier includes a first transmission line for input, a second transmission line for output, an input termination resistor connecting a line end of the first transmission line and a power supply voltage, an output termination resistor connecting an input end of the second transmission line and a ground, unit cells having input terminals connected to the first transmission line and output terminals connected to the second transmission line, and a bias tee configured to supply a bias voltage to an input transistor of each of the unit cells. An emitter or source resistor of the input transistor of each of the unit cells is set to a different resistance value from each other in order for a collector or drain current flowing through the input transistor of each of the unit cells to have a uniform value.

A first phase adjuster adjusts the phase of any one of first and second AC voltages generated in a negative resistance circuit so that a shift amount &#x3a6; in a first variable phase shifter falls within a range of 0 degrees&#x2264;&#x3a6;&#x3c;180 degrees, and outputs the phase-adjusted AC voltage to the first variable phase shifter, and a second phase adjuster adjusts the phase of the other one of the first and second AC voltages generated in the negative resistance circuit so that a shift amount &#x3a6; in a second variable phase shifter falls within a range of 0 degrees&#x2264;&#x3a6;&#x3c;180 degrees, and outputs the phase-adjusted AC voltage to the second variable phase shifter.

Voltage-controlled oscillator

In a distributed amplifier, a plurality of cascode amplifiers connected in parallel between an input side transmission line and an output side transmission line are provided, a transmission line is connected to an input terminal of an output transistor of each of the amplifiers, and a bias potential is applied from a bias circuit to the input terminal of the output transistor via the transmission line.

Distributed amplifier

A digital signal process unit includes a first cancel signal generation unit and a second cancel signal generation unit. The first cancel signal generation unit generates, as a first cancel signal component, a cancel signal component corresponding to an image signal included in an analog signal output from a mixer. The second cancel signal generation unit generates, as a second cancel signal component, a cancel signal component corresponding to a leakage signal generated between an input and output of the mixer. The digital signal process unit includes subtractors for subtracting the first cancel signal component and the second cancel signal component from a signal component corresponding to a frequency band divided from an input signal to obtain a digital signal.

Signal generator and signal generation method

A wide-band analog input signal is converted into a digital output signal on the basis of a band division method without the need for filter circuits. An analog processing block A(j=2 to N, where N is an integer) down-converts an analog input signal Susing a cutoff frequency fj-of a channel CHand A/D-converts an analog signal Sacquired as a result. A digital processing block Bdoubles the signal strength of a first digital signal Sacquired by A, subtracts a third digital signal Sof the channel CHfrom a second digital signal Sacquired as a result, up-converts the acquired third digital signal Susing the cutoff frequency f, and outputs the result to an adder as a channel output signal Sof a corresponding channel CH.

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Tokyo, Japan

Teruo Jo