Fujitsu Corporation

Teruo Ishihara

Yukito Tsunoda

Ryuta Tanaka

Takuji Yamamoto

Akira Ito

Hiroshi Nakao

Mitsuru Tomono

Katsuhiro Yoda

Makiko Ito

Hisanori Fujisawa

Toru Tsuruta

Takahiro Notsu

Nobuyuki Iwasaki

Norichika Kumamoto

Hisanao Akima

Ritsuko Tanaka

Hideaki Fukuda

Masayuki Hiromoto

Hideki Yosizawa

A computer includes: a memristor array including memristors arranged at intersections between word lines and a first bit line in the memristor array and at intersections between the word lines and second bit lines in the memristor array; an adder circuit configured to obtain sum voltages for the second bit lines by adding first voltages generated according to currents that flow in the second bit lines when a first pattern is supplied to the word lines to difference voltages between a reference voltage generated according to a current that flows in the first bit line when a second pattern is supplied to the word lines and second voltages generated according to currents that flow in the second bit lines when a second pattern is supplied to the word lines; and a detection circuit that detects a second bit line that corresponds to a maximum value of the sum voltages.

Computer and calculation method using memristor array

An arithmetic processing apparatus includes a memory and a processor. The processor coupled to memory and configured to determine an individual not to be evolved to an individual of a second generation from among a plurality of individuals in a first generation based on a predetermined reference for calculation completion of fitness calculation for each of the plurality of individuals, the second generation being a generation next to the first generation, and determine to cause the determined individual to evolve to an individual of a generation next or subsequent to the second generation.

Arithmetic processing apparatus, non-transitory computer-readable storage medium, and arithmetic processing method

An operation processing device includes: a memory; and a processor coupled to the memory and configured to: acquire statistical information on distribution of bits in fixed point number data after execution of an instruction on the fixed point number data; and update a decimal point position of the fixed point number data.

Operation processing device, information processing device, and information processing method

The reconfigurable circuit of the present invention in which time division multiple processing is possible has a pipeline structure with the number of stages of an integral multiple of a given number, and comprises a plurality of processor elements having a processing unit whose configuration is variable according to first configuration data to be supplied, a network in which all inputs and outputs of a plurality of said processor elements are connected and which transfers data by one clock between the input and output according to second configuration data to be supplied, and a switching unit which cyclically switches by one clock and supplies the first and second configuration data prepared for the given number of tasks to each of the processing units.

Reconfigurable circuit having a pipeline structure for carrying out time division multiple processing

The present invention relates to a multiprocessor system, which comprises two or more processor elements to be executed by a common program, a control section for switching such plural processor elements one from another for execution by the common program, and a storing section storing handover information relating to the common program which information is to be handover from the one processor element to the another processor element. This not only optimizes each of the functions of the processor elements, but also achieves certain delivery or interchange of the information between these process or elements, and even reduces the power consumption.

Multiprocessor system, multiprocessor control method, and multiprocessor control program retaining computer-readable recording medium

A data array forming circuit replaces part of software operation in a low bit rate coding system. The circuit includes a memory storing plural kinds of basic data groups, and an address generating circuit generating an address to access the memory. A data array is formed in accordance with input speech data by selectively reading plural kinds of blocks out of the basic data groups according to the address and by combining the plural read blocks containing different quantities of words. Each block contains an arbitrary quantity of word data. In a data sorting circuit to replace part of software operation in a low bit rate coding system, an index corresponding to the data is set with an initial value on initiating the sorting operation, and a value incremented successively from the initial value is set as an index of the next data. In a convolution coding circuit, test data are set in parallel into the shift register, by providing each input terminal of shift register flip-flops with a selector having two input terminals. One terminal is input with test data, or each flip-flop may be provided with a preset terminal and a clear terminal, where a preset signal according to the test datum is input to the preset terminal, and a clear signal is input to the clear terminal.

Low bit rate coding system for high speed compression of speech data

An echo canceller system for performing echo cancelling processing on a plurality of cells on a transmission line includes a plurality of echo canceller units to which the cells applied to the echo canceller system are allocated according to an applied order of the cells regardless of channels of the cells.

Echo canceller system in an ATM network

An image data quantizing circuit that quantizes image data through the use of a 2-port RAM and a quantizing ROM. Pixel data stored in the 2-port RAM functions as an address for the quantizing ROM. The quantized output of the quantizing ROM is stored in the 2-port RAM.

Image data quantizing circuit with a memory for storing unquantized and

A scan converter control circuit includes first and second memories, each having a data write mode and a data read mode which are selected in response to a switching signal so that the first memory is in the data write mode when the second memory is in the data read mode and the first memory is in the data read mode when the second memory is in the data write mode. A write address counter generates a write address which is to be alternately supplied to the first and second memories and generates a write completion signal when the write address becomes equal to a predetermined count value. A read address counter generates a read address which is to be alternately supplied to the first and second memories and generates a read completion signal when the read address becomes equal to a predetermined count value. A data input controller enables the write address counter in response to a data input signal supplied from an external circuit and disables the write address counter when receiving the write completion signal. A memory switching controller generates the switching signal having a logic value which is changed in response to the write completion signal. A data output controller enables the read address counter in response to the write completion signal and disables the read address counter in response to the read completion signal.

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Kawasaki, Japan

Teruo Ishihara