Fujitsu Corporation

Terunobu Maruyama

Hiroyuki Sugiyama

Miki Takagi

Noriyuki Ito

Yasunori Abe

Tadashi Konno

Hiroshi Ikeda

Yoshiyuki Kato

Ryoichi Yamashita

Takeo Nakamura

Tomoyuki Isomura

Hiroji Takeyama

Naomi Bizen

Mitsuru Yasuda

Ryouichi Yamashita

Mitsuru Satou

Yuki Kumon

Keiko Ohsawa

Yaroku Sugiyama

The time and trouble of a mismatch cause analysis after logical equivalence verification can be reduced, and design and verification TAT can be shortened. A logical equivalence verifying device performs logical equivalence verification between two circuits, and displays the result of the logical equivalence verification. A preprocessing sectionperforms structural matching so as to determine whether there are portions corresponding in circuit structure to each other in corresponding logic cones of the two circuits. An internal DBrecords the results of the structural matching as an identifier for each element. A subcone extracting sectionextracts, as a subcone, a collection of elements, which are mutually to one another and have the same identifier, from each logic cone. A verifying sectionperforms logical equivalence verification between the two circuits for each of the extracted subcones. A display control sectiondisplays only those subcones for which the logical equivalence verification has resulted in mismatch.

Logical equivalence verifying device, method, and computer-readable medium thereof

Logical equivalence verifying device, method and computer readable medium thereof

A cell arrangement evaluating method for predicting a wiring density based on only a cell arranging result prior to initiation of any wiring programs so as to easily perform wiring condition evaluation based on the wiring density within a short time. Two cells to be connected by wiring are selected, and a rectangular region is obtained in which the pins of the two cells to be connected are diagonal verfexes. The probability of wiring between the pins to be connected passing through a certain grid point of wiring grid is calculated. A proportion of the rectangular region occupying each evaluation unit grid is calculated, and then, for each evaluation unit grid, an index for an increase of a wiring density made by the factor of the wiring in the evaluation unit grid is calculated. Then, for each evaluation unit grid, the sum of indexes calculated for all the wiring lines among the cells as a wiring density in the evaluation unit grid is calculated. The cell arrangement evaluation method is used for designing an integrated circuit such an LSI or a circuit on a printed circuit board.

Cell arrangement evaluating method, storage medium storing cell arrangement evaluating program, cell arranging apparatus and method, and storage medium storing cell arranging program

A circuit designing apparatus of an interactive type which enables a simplified and highspeed circuit design process while largely reducing a burden on a designer, having a speed analyzing unit for conducting a delay computation for each wiring path on a circuit to be designed and a display control unit for displaying a result of the delay computation by the speed analyzing unit on a display unit. When the speed analyzing unit conducts a delay computation, a delay value of each logic component forming the circuit that is an object of the design is set and altered according to a dullness of a signal waveform inputted to the logic component. The circuit designing apparatus of an interactive type may be applied to a system for conducting a circuit design of an integrated circuit such as an LSI or the like or a printed circuit board.

Interactive circuit designing apparatus which displays a result of component placement and wire routing from a layout design unit

A circuit element placement method and apparatus in which circuit elements can surely be placed in a short time even if a circuit scale is increased. For this purpose, there is sequentially executed a first step of determining placement coordinates of sequential logic circuit elements among many circuit elements to be placed and a second step of determining placement coordinates of circuit elements other than the sequential logic circuit elements with consideration given to the placement coordinates of the sequential logic circuit elements, determined in the first step. The method and apparatus are applicable at a time of design of an integrated circuit such as LSI, or a circuit on a printed wiring board.

Method and apparatus for determining locations of circuit elements including sequential circuit elements

A packaging design system for an LSI circuit includes: a gate placement preparation unit for preparing basic placement data for gates used as an original data for producting the LSI circuit; a wiring data preparation unit operatively connected to the gate placement preparation unit for preparing wiring data based on wiring patterns each having the same length between gates; a delay calculation unit operatively connected to the wiring data preparation unit for calculating net delays between gates and path delays from a clock input until an output in the LSI circuit; a standard path delay determining unit operatively connected to the delay calculation unit for determining a standard path delay in accordance with distribution of path delays; and a macro determining unit operatively connected to the standard path delay determining unit for selecting the macros in accordance with predetermined conditions of path delays, and selected several macros being used for an actual placement of gates.

Packaging design system for an LSI circuit

A circuit designing apparatus of an interactive type which enables a simplified and high-speed circuit design process while largely reducing a burden on a designer, having a speed analyzing unit for conducting a delay computation for each wiring path on a circuit to be designed and a display control unit for displaying a result of the delay computation by the speed analyzing unit on a display unit. When the speed analyzing unit conducts a delay computation, a delay value of each logic component forming the circuit that is an object of the design is set and altered according to a dullness of a signal waveform inputted to the logic component. The circuit designing apparatus of an interactive type may be applied to a system for conducting a circuit design of an integrated circuit such as an LSI or the like or a printed circuit board.

Circuit designing apparatus of an interactive type

The invention provides an interactive circuit designing apparatus wherein a logic design, a layout design and a speed analysis can cooperate with each other in processing. The interactive circuit designing apparatus comprises a logical designing section for logically designing a design object circuit, a layout designing section for performing mounting arrangement of logical components constituting a design object circuit based on a result of the logical design and performing wiring between the logical components, and a speed analysis section for performing a speed analysis based on calculation of a delay for each of paths on the design object circuit in accordance with a result of the layout. The logical designing section, the layout designing section and the speed analysis section are connected to each other so as to cooperate with each other when necessary. The interactive circuit designing apparatus is applied to an apparatus for designing a circuit of an LSI, a printed circuit board or a like element.

Interactive circuit designing apparatus

Growing community of inventors

Kawasaki, Japan

Terunobu Maruyama