Nippon Gakki Seizo Kabushiki Kaisha

Yamaha Corporation

Terumoto Nonaka

Tadahiko Hotta

Yasunori Mochida

Shin Yamashita

Jun-ichi Nishizawa

Kenzaburou Iijima

Takashi Yoshida

Yoshinori Hayashi

Akira Usui

Seiya Nishimura

Takeshi Matsuyama

Osamu Hanagasaki

Yuoshinori Hayashi

Katsuyuki Yokoi

A semiconductor integrated circuit device comprises a semiconductor chip with a plurality of standard cells formed thereon. Each of said standard cells consists of at least one type of standard cell which is selected from among a plural types of standard cells which are pre-registered in a standard cell library retained by a computer. The placement and routing pattern of said standard cells on said semiconductor chip are designed automatically by a computer system. In relation to at least one of said standard cells, at least one basic cell for general-purpose logical gate is formed on said semiconductor chip to deal with design modification of the device.

Semiconductor integrated circuit device made by a standard-cell system

An absolute displacement detector utilizing two sensors and a code bearing track having domains arranged such that relative movement between the sensors and the track produces two signals in phase quadrature which are processed with digital circuitry to provide displacement data indicated by a multiple bit digital word whose higher bits indicate number of domains passed and whose lower bits indicate position within a domain.

Displacement detector for an encoder

A magnetoresistive detection head for detecting relative displacement of a magnetic recording medium relative to the detection head includes two sets of magnetoresistive elements which change their respective resistances in response to changes in the intensity of a magnetic field generated by the magnetic recording medium during the relative displacement. The magnetoresistive elements are overlapped and spaced relative to each other by a specified space lag in the direction of the relative displacement. One set of magnetoresistive elements produce a sine output and the other a cosine output. The overlapping and precise spacing of the elements aligns the phases of the signal envelopes of the sine and cosine outputs, reducing reading errors when physical warps appear on the magnetic recording medium.

Overlapped magnetoresistive displacement detecting transducers having

A semiconductor integrated circuit comprising a plurality of vertical static induction transistors (SITs) of normally-off type formed in a common semiconductor substrate in such a manner that the lateral dimension of the channel region of the SITs employed to form a hardware circuit region such as a logic circuit is designed greater than of the SITs which are employed to form a peripheral circuit region. Thus, it is possible to provide a semiconductor integrated circuit which concurrently satisfies a plurality of differently functioning semiconductor circuit requirements to exhibit different electric characteristics as represented by a high-speed operation and a high breakdown voltage.

Semiconductor integrated circuit incorporating SITS

A semiconductor integrated logic circuit comprises a load transistor having a carrier injecting region and a carrier extracting region and an inverter transistor having a source region, drain regions, channel regions each connected between the source region and each of the drain regions, and gate regions defining the respective channel regions therebetween. The extracting region is merged into the gate regions. The channel regions have such dimensions and an impurity concentration that the channels are closed with depletion layers extending from the gate regions at zero gate voltage. The gate regions constitute a logic input and the drains constitute logic outputs. The zero gate voltage renders the channels non-conductive and the raised voltage renders the channels conductive, thus realizing an inverter circuit useful for wired logics.

Multi-drain enhancement JFET logic (SITL) with complementary MOSFET load

A digital semiconductor integrated circuit device comprising a common semiconductor substrate, a dynamic MOS circuit block composed mainly of a MOS-FET, and a static bipolar circuit block composed of a bipolar transistor or an SIT which is operated in a 'bipolar mode' and cascade-connected to said dynamic MOS circuit block in said common semiconductor substrate, and arranged to be operative so that, by setting the timing of clock pulses, the logical operations of these circuit blocks are performed in a timed relationship with each other. Thus, this integrated circuit device can be produced with minimized dependency of its operation velocity upon the design of these circuit blocks and can perform a high-speed operation and can provide a high packing density.

Dynamic MOS circuit block and static bipolar transistor circuit block

A method of making a semiconductor integrated circuit on a semiconductor substrate containing thereon an SIT and an IG(MOS) FET or an SIT and C-MOS FETs, comprises a series of steps of making these functional semiconductor devices many of which steps are rendered to be common to the SIT and the FET. The gate region of said IG(MOS) FET is formed as a semiconductor gate layer which typically is made of polycrystalline silicon, and an active semiconductor area of said IG(MOS) FET is formed by using this semiconductor gate layer as the mask therefor.

Method of making semiconductor integrated circuit

A method of manufacturing an SIT or SITL device, comprising simultaneous formation of a gate doping aperture and contact apertures for a source and a drain. Firstly, a gate region is doped through the doping aperture with the contact apertures being covered by a mask. Then, a source region is doped so as to be in self-alignment relation relative to the gate region and a source contact portion is doped so as to be in self-alignment relation relative to the source region and the gate region, whereby the mask alignments are eliminated and packing density is enhanced.

Method of manufacturing semiconductor device

A reference frequency generator for a tuning apparatus comprising a variable frequency divider which frequency divides a source signal in accordance with frequency division data stored in one or more ROM's. The frequency division data comprises note data for specifying frequencies of respective notes in one octave of a musical scale, pitch deviation data for specifying pitch deviation of the respective notes in one octave with respect to the frequencies specified by said note data and tuning curve data for specifying tuning characeristics covering several octaves, so that the generator generates reference frequency signals representing various pitch deviations and tuning characteristics as well as a standard tuning pitch or characteristic.

Reference frequency signal generator for tuning apparatus

In an integrated injection logic (IIL) type semiconductor integrated circuit, an injector transistor is formed with a field effect transistor (FET) and an inverter transistor is formed with a bipolar transistor (BPT). The drain region of the FET is merged into the base region of the BPT. The base of the BPT constitutes a logic input and the collector of the BPT constitutes a logic output. The FET may be either of the junction type or of the insulated gate type. The carrier injection efficiency can be improved to approximately unity over a wide range of the injection current.

IIL Type semiconductor integrated circuit

An integrated logic circuit arrangement comprising: an input junction field effect transistor having at least one source for receiving a digital input signal, a drain to which a load is connected, and gate held at a reference potential, said junction field effect transistor being operative to effect switching operation in accordance with said digital input signal; and an output bipolar type transistor having its base connected to said drain to effect switching operation in accordance with an output signal delivered from said drain. This integrated logic circuit arrangement provides high speed logic operation, low power dissipation and high integration density.

Integrated logic circuit arrangement

In a semiconductor device of the type arranged so that the minority carriers are injected into a lightly-doped n type semiconductor layer from a heavily-doped p type semiconductor layer provided in the n type layer, that portion of the p type layer excluding a certain portion is separated from the n type layer by a separator layer to cause the p type layer to contact the n type layer only at the certain portion, whereby the carrier injection is restricted to occur within a limited region of the n type layer contacting the certain portion of the p type layer. The separator and the p type layer are formed, by relying on a self-alignment technique using a double-mask layer, as diffused regions partially overlapping each other with a good relative alignment in the n type layer.

Semiconductor device and manufacturing process thereof

A field effect transistor of the type wherein the conductivity of the channel thereof is variable by injecting the minority carriers into the channel from the gate thereof, is disclosed. The channel of the transistor includes minority carrier recombination centers in such an amount that the lifetime of the minority carriers in the channel may be shortened so as to sufficiently reduce the minority carrier storage effect in the channel. The recombination centers may comprise elements such as gold doped in the channel region. This field effect transistor is hardly subject to the minority carrier storage effect and is capable of effecting a turn-off action at a markedly high speed.

Jsit-type field effect transistor with deep level channel doping

An integrated semiconductor device including at least one first vertical-type junction field effect transistor (vertical JFET) having a triode-like unsaturated voltage-current characteristic and at least one second vertical JFET having a bipolar-transistor-like saturated voltage-current characteristic, both being integrally formed in a semiconductor body. Both the first and second vertical JFET are much similar in general arrangement to each other, thus allowing simultaneous forming thereof by the same manufacturing process, without sacrificing the good characteristics of these two types of transistors.

Integrated semiconductor device

In an integrated semiconductor device of the IIL type which includes a switching transistor and an injector transistor for supplying carriers to drive the switching transistor, the switching transistor is a static induction transistor which comprises: cylindrical current channels for providing current paths between a source and drains; a control gate surrounding the outer boundaries of the channels to form pn junctions therebetween and being injected with carriers from the injector transistor to control the current flow in the channels; and floating gates disposed inside the respective channels to form pn junctions therebetween. The floating gates are electrically floating and have a potential affected by the potential of the control gate to contribute to the channel conduction controlling action together with the control gate.

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Hamamatsu, Japan

Terumoto Nonaka