Hitachi, Ltd.

Hitachi Engineering Co., Ltd.

Hitachi Microcomputer Engineering, Ltd.

Terumine Hayashi

Kazumi Hatayama

Ikuro Masuda

Hiroshi Date

Hideo Maejima

Mitsuji Ikeda

Shigeo Kuboki

Shoichi Watanabe

Jiro Kusuhara

Hiromi Tanaka

Takashi Natabe

Yasuyuki Fujihara

Takayuki Takei

Yutaka Sekiyama

Toshiaki Masuda

In order to determine the routes of wiring connections on a multi-layer circuit board, to form a suitable wiring pattern without local congestions of the wiring connections, the wiring region of the circuit board is considered as one or more areas. For each area, a preferred wiring direction is determined for each layer of the circuit board. Those preferred directions for the layers may be determined by proposing initial preferred wiring directions for each layer, determining whether there is congestion of the wiring connections in any area, and changing the wiring direction for one or more layers of such an area to reduce the congestion. Alternatively, the wiring directions can be determined for each layer without there being an initial wiring direction which is common to all areas. Furthermore, an excess number value may be obtained, which is the sum by which the desired number of wiring connections of an area exceed a predetermined value, for a series of candidate wiring directions of the layers of the area, and then the candidate is selected which has the minimum excess value.

Method of determining routes for a plurality of wiring connections and a

The first and second flip-flop circuits are connected in series included within a combinational logic for carrying out a delay test. The first and second flip-flop circuits are provided with control pins, system clock pins, scan clock pins, system data pins and scan data pins, respectively. A delay time propagated from the first flip-flop circuit to the second flip-flop circuit through the path of the combinational logic to be tested is measured by detecting an input time to the first flip-flop circuit by the system clock signal to the first flip-flop circuit in response to an input signal to the control pins and a time stored in the second flip-flop circuit corresponding to output system data from the first flip-flop circuit. By measuring the delay time, whether the combinational logic is normal or abnormal is detected.

Logic circuit with additional circuit for carrying out delay test

A method of finding the optimal placement of circuit elements is disclosed in which the optimal position of each circuit element is determined from the results of arithmetic operations performed by a processor network where a plurality of processors are interconnected so as to form a neural network, and each processor takes in its own output and the outputs of all other processors to solve a problem.

Placement optimizing method/apparatus and apparatus for designing

Element placement optimizing method and apparatus for determining an optimum placement of constituent elements for an LSI or the like. A parallel processing type computer system including a plurality of CPUs is used. An initial element placement is established and a number of paired element candidates for position exchange are selected from the initial placement, the number being equal to that of CPUS. A cost improvement value resulting from the exchange is determined for each of the paired candidates by the associated CPU. The exchange of the elements is performed for the paired element candidates for which the cost improvement value is maximum of those determined by the CPUs. By repeating the exchange, an optimum element placement is determined.

Method and apparatus for optimizing element placement and method and

A method is provided for manufacturing a master slice semiconductor integrated circuit device. Initially, a first total circuit diagram which is to be reformed into a master slice semiconductor integrated circuit device is defined. First and second circuit points on the first total circuit block which are to be used respectively as input and output terminals of the master slice semiconductor integrated circuit device are specified. Next, signal transmitting paths are successively traced from the output to the input of each logic gate located in the signal transmitting paths in actual use. In the course of the tracing, these traced gates are marked and the logic gates actually in use are identified. As a result, in addition to those logic gates having unused output terminals, the gates constituting a closed loop isolated from the signal transmitting paths for transmitting substantial output signals are identified as unnecessary gates and deleted. Further, gates outputting only a fixed value are determined and designated unnecessary gates which are also deleted.

Method for deleting unused gates and method for manufacturing

A memory incorporating logic Large Scale Integration (LSI) and a method for testing the same LSI includes signal path switching circuit portions which are disposed in the paths of a memory portion and a logic circuit portion. A test signal input and an output signal can be observed at an input and output terminal portion so as to be able to effect a dynamic function test of the memory portion. Further there is disposed a logic circuit test signal memory circuit portion, which switches over the signal path switching circuit portions to the logic circuit portion so as to be able to effect a test of the logic circuit portion, independently of the state of the memory portion.

Memory incorporating logic LSI and method for testing the same LSI

Disclosed is a method of level sensitive testing of a logic array system and an LSI chip having testing means incorporated therein. The present invention is especially suitable for testing a RAM and the function of a logic unit which is a functional peripheral of the RAM. The LSI chip comprises means for selecting a specific address of the RAM, means for writing a signal at the specific address of the RAM and reading out the data from the specific address of the RAM, and means for selecting the operation of the chip between a usual operation mode and a scan-in/scan-out diagnostic mode for testing the RAM or functional peripheral of the RAM. Testing can be easily conducted by addition of a small number of logic elements. The larger the number of address signal lines and the number of data signal lines of the RAM, the more effective the testing method becomes.

Method and apparatus for diagnosing a LSI chip

An integrated circuit device comprises combinational circuits and sequential circuits. Each of the sequential circuits is provided with a (common) input control signal terminal for controlling the entry of main input terminal signals into the sequential circuit, a test data input/output terminal, a read/write signal terminal for controlling the transfer of the test data, and a latch circuit. The integrated circuit device is partitioned into sequential circuit groups, and combinational circuit groups used as partitioning test units, the main input/output terminal groups of which are connected with the sequential circuit groups through wiring layers. Test data are written into and read out from the sequential circuit groups under control of read/write signal lines through bus lines dedicated to testing. Thus, a higher fault-coverage ratio can be easily obtained with a smaller number of steps and a small test circuit area.

Integrated circuit device

A method of diagnosing an integrated circuit device having a plurality of combinational circuits, at least one input memory circuit connected to an input side of the combinational circuits, and an output memory circuit connected to an output side of the combinational circuits is disclosed. An input diagnostic signal is selectively applied to at least one input memory circuit connected to a given one of the combinational circuits, to read out a diagnostic signal stored in an output memory circuit connected to the given combinational circuit. Further, an integrated circuit device is disclosed which is suited to be diagnosed in the above method.

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Hitachi, Japan

Terumine Hayashi