Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Teruhito Ohnishi

Akira Asai

Tohru Saitoh

Takeshi Takagi

Koichiro Yuki

Ken Idota

Yoshihiro Hara

Yoshihiko Kanzawa

Shigeki Sawada

Takahiro Kawashima

Minoru Kubo

Gaku Sugahara

Haruyuki Sorada

Tetsuya Ueda

Katsuya Nozawa

Kenji Toyoda

Hiroshi Nishimura

Masanori Fukumoto

Yoshihisa Minami

Keiichiro Shimizu

Kohsaku Yano

Tsuneichiro Sano

Tomofumi Shono

Taizo Fujii

Koichi Hasegawa

Mitsuo Sugiura

Masayuki Endo

Atsushi Nakamura

Akira Inoue

Noboru Nomura

Paul A Clifton

Shinichiro Hayashi

Koji Katayama

Michikazu Matsumoto

Yuichi Miyoshi

Yo Ichikawa

Yoshinori Odake

Shigetaka Aoki

Minoru Fujii

Hidenori Notake

An inductor includes a flat substrate and a conductor in a spiral shape having a plurality of turns. The plane on which the conductor is formed is substantially in parallel with a principal surface of the substrate. The turns of the conductor are equally spaced from each other in a direction parallel to the plane on which the conductor is formed. An outer one of the turns of the conductor is wider and thinner than an inner one of the turns of the conductor. A level of at least one of a top and a bottom of the conductor differs from one turn to another in a cross section vertical to the plane on which the conductor is formed.

Inductor and method for fabricating the same

A bipolar transistorcomprises a substrate, a intrinsic base regionand an extrinsic base region. The intrinsic base regioncomprises a silicon buffer layercomprised of silicon which is formed on the substrate, and a composition-ratio graded base layerwhich is formed on the silicon buffer layer and comprises silicon and at least germanium and where a composition ratio of the germanium to the silicon varies in a thickness direction of the composition-ratio graded base layer. The extrinsic base regioncomprises an extrinsic base formation layercomprised of silicon which is formed on the substrate and adjacent to the silicon buffer layer. And the thickness of the extrinsic base formation layeris not less than 40 nm.

Heterojunction biploar transistor and method for manufacturing same

A bipolar transistor includes a Si single crystalline layer serving as a collector, a single crystalline Si/SiGeC layer and a polycrystalline Si/SiGeC layer which are formed on the Si single crystalline layer, an oxide film having an emitter opening portion, an emitter electrode, and an emitter layer. An intrinsic base layer is formed on the single crystalline Si/SiGeC layer, part of the single crystalline Si/SiGeC layer, the polycrystalline Si/SiGeC layer and the Co silicide layer together form an external base layer. The thickness of the emitter electrode is set so that boron ions implanted into the emitter electrode and diffused therein do not reach an emitter-base junction portion.

Bipolar transistor and method for fabricating the same

On an Si substrate, a buffer layer, a SiGe layer, and an Si cap layerare formed. A mask is formed on the substrate, and then the substrate is patterned. In this manner, a trenchis formed so as to reach the Si substrateand have the side faces of the SiGe layerexposed. Then, the surface of the trenchis subjected to heat treatment for one hour at 750&#xb0; C. so that Ge contained in a surface portion of the SiGe layeris evaporated. Thus, a Ge evaporated portionhaving a lower Ge content than that of other part of the SiGe layeris formed in part of the SiGe layerexposed at part of the trench. Thereafter, the walls of the trenchare oxidized.

Semiconductor device

The bipolar transistor of the present invention includes a Si collector buried layer, a first base region made of a SiGeC layer having a high C content, a second base region made of a SiGeC layer having a low C content or a SiGe layer, and a Si cap layerincluding an emitter region. The C content is less than 0.8% in at least the emitter-side boundary portion of the second base region. This suppresses formation of recombination centers due to a high C content in a depletion layer at the emitter-base junction, and improves electric characteristics such as the gain thanks to reduction in recombination current, while low-voltage driving is maintained.

Heterojunction bipolar transistor having reduced driving voltage requirements

A method of estimating substrate temperature according to this invention includes the steps of epitaxially growing a Si-containing layer () on a SiGe layer () formed on a substrate for temperature estimation () constituted of a Si substrate under a reaction control condition; finding a relationship between a rate of growth of the Si-containing layer and a substrate temperature of the substrate for temperature estimation; epitaxially growing a Si-containing layer on a substrate for device fabrication as a subject of substrate temperature estimation under a reaction control condition; and estimating a substrate temperature of the substrate for device fabrication based on the rate of growth of the latter Si-containing layer and the relationship between the rate of growth of the former Si-containing layer () and the substrate temperature of the substrate for temperature estimation.

Method of estimating substrate temperature

Immediately after a Si/SiGe film containing a contaminant is formed over all surfaces of a substrate by epitaxial growth, a portion of the Si/SiGe film formed to the back surface side of the substrate is removed by wet etching. In addition, the Si/SiGe film is subjected to processing with heating in a container, after which a dummy run is carried out in the container. These processings prevent secondary wafer contamination through a stage, a robot arm or a vacuum wand for handling a wafer and the contamination of the container also used in the fabrication process of a semiconductor device free from any group IV element but Si.

Method for fabricating semiconductor device

A SiGelayerfunctioning as the base composed of an i-SiGelayer and a pSiGelayer is formed on a collector layerand a Si cap layeras the emitter is formed on the pSiGelayer. An emitter lead electrodewhich is composed of an npolysilicon layercontaining phosphorus in a concentration equal to or lower than the solid-solubility limit for single-crystal silicon and a npolysilicon layercontaining phosphorus in a high concentration, is formed on the Si cap layerin a base openingThe impurity concentration distribution in the base layer is properly maintained by suppressing the Si cap layerfrom being doped with phosphorus (P) in an excessively high concentration. The upper portion of the Si cap layermay contain a p-type impurity. The p-type impurity concentration distribution in the base layer of an NPN bipolar transistor is thus properly maintained.

Bipolar transistor device having phosphorous

A method for fabricating a semiconductor crystal that has a first step for forming a semiconductor crystal layer () that contains carbon atoms and at least one kind of Group IV element other than carbon on a substrate (), a second step for adding an impurity that is capable of reacting with oxygen to the semiconductor crystal layer (), and a third step for removing the carbon atoms contained in the semiconductor crystal layer () by reacting the carbon with the impurity. This method makes it possible to fabricate a semiconductor crystal substrate in which the concentration of interstitial carbon atoms is satisfactorily reduced, thus resulting in excellent electrical properties when the substrate is applied to a semiconductor device.

Method of producing semiconductor crystal

A SiGe spacer layera graded SiGe base layerincluding boron, and an Si-cap layerare sequentially grown through epitaxial growth over a collector layeron an Si substrate. A second deposited oxide filmhaving a base opening portionand a P+ polysilicon layerthat will be made into an emitter connecting electrode filling the base opening portion are formed on the Si-cap layerand an emitter diffusion layeris formed by diffusing phosphorus into the Si-cap layerWhen the Si-cap layeris grown, by allowing the Si-cap layerto include boron only at the upper part thereof by in-situ doping, the width of a depletion layeris narrowed and a recombination current is reduced, thereby making it possible to improve the linearity of the current characteristics.

Bipolar transistor and fabrication method thereof

The present invention discloses a process of fabricating a semiconductor device comprising the steps of: forming a collector layer of a first conductivity type at a portion of a surface of a semiconductor substrate; forming a collector opening portion in a first insulating layer formed on the semiconductor substrate; epitaxially growing, on the semiconductor substrate of the collector opening portion, a semiconductor layer including a layer of a second conductivity type constituting a base layer; sequentially layering, on the semiconductor substrate, an etching stopper layer against dry etching and a masking layer against wet etching; exposing a part of the etching stopper layer by removing a part of the masking layer by means of dry etching; and by subjecting the exposed etching stopper layer to a wet etching treatment using the remaining masking layer as a mask, forming a base junction opening portion through the etching stopper layer and the masking layer.

Method of fabricating a bipolar transistor utilizing a dry etching and a wet etching to define a base junction opening

A semiconductor device and a method of fabricating the same according to this invention are such that: a gate insulator is formed over a predetermined region of a semiconductor substrate; a gate electrode is formed on the gate insulator; source and drain regions respectively formed in portions of the predetermined region that are situated on both sides of the gate electrode in plan view; a body region formed by a region of the predetermined region exclusive of the source and drain regions; and a contact electrically interconnecting the gate electrode and the body region, wherein a portion of the contact which is connected to the gate electrode is formed to intersect the gate electrode in plan view.

A variable capacitance device comprising, in a semiconductor layer formed on a substrate via an buried oxide film: an n&#x2212; regionformed in the shape of a ring and containing an n-type dopant; an anodeadjoined to the outer periphery of the n&#x2212; regionthe anodebeing formed in the shape of a ring and containing a p-type dopant; and a cathodeadjoined to the inner periphery of the n&#x2212; regionthe third region containing an n-type dopant, wherein the dopant concentration in the n&#x2212; regionis lower than that in each of the anodeand the cathode

Variable capacitance device and process for manufacturing the same

On an Si substratea buffer layera SiGe layerand an Si cap layerare formed. A mask is formed on the substrate, and then the substrate is patterned. In this manner, a trenchis formed so as to reach the Si substrateand have the side faces of the SiGe layerexposed. Then, the surface of the trenchis subjected to heat treatment for one hour at 750&#xb0; C. so that Ge contained in a surface portion of the SiGe layeris evaporated. Thus, a Ge evaporated portionhaving a lower Ge content than that of other part of the SiGe layeris formed in part of the SiGe layerexposed at part of the trench. Thereafter, the walls of the trenchare oxidized.

Growing community of inventors

Osaka, Japan

Teruhito Ohnishi