Hitachi, Ltd.

Teruhisa Shimizu

Takeshi Kato

Katsuya Tanaka

Masamori Kashiyama

Fumio Yuuki

Nobuo Yosida

A processor or a semiconductor integrated circuit has circuit blocks performing signal processing, internal power supply nets, noise detecting circuits corresponding to each circuit block that detect noise on the power supply nets and an interruption handling circuit that prevents a malfunction in processing within a circuit block caused by noise on the power supply nets. When noise is detected, the interruption handling circuit performs an interruption by sending an interruption signal to the circuit block relating to the signal processing for preventing a malfunction to the circuit block. During the operation of a plurality of stages for executing an instruction, noise is monitored at every stage. If no noise is detected through a final stage, the result is outputted. If noise is detected at any one of the stages, then an interruption process is performed.

Semiconductor integrated circuit having noise detect circuits detecting noise on power supply nets

A clock distributing logic for distributing a clock signal in a circuit and reducing clock skew which occurs during the distributing of the clock signal in the circuit and a method for designing the same. The clock distributing logic includes at least two stages of clock amplifying gates for distributing the clock signal to source and sink sides of the circuit. Each of the at least two stages are successively connected to each other. Further, each of the at least two stages except a last stage includes clock amplifying gates of a same size providing a same driving ability. The last stage of clock amplifying gates includes clock amplifying gates of different sizes providing different driving abilities. The size of each clock amplifying gate of the last stage of clock amplifying gates is set to make the delay in distributing the clock signal in the circuit coincide with a desired clock signal distributing cycle.

Clock distributing logic and clock skew control design method for

A memory management unit is capable of judging that a specific bit has been partially rewritten by checking it against a dummy bit stored in a tag memory which is included in the memory management unit and thus correcting a parity bit. Accordingly, it is possible to accurately execute a parity check operation and it is also possible to improve the throughput of the memory management unit and hence promote lowering in the cost.

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Ome, Japan

Teruhisa Shimizu