Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Panasonic Semiconductor Solutions Co., Ltd.

Panasonic Intellectual Property Management Co., Ltd.

Teruhisa Ikuta

Yoshinobu Sato

Hiroyoshi Ogura

Hisao Ichijo

Toru Terashita

Masaaki Noda

Hiroshi Sakurai

Satoru Kanai

Akira Fukumoto

Yoshinobu Satou

In a semiconductor device including first and second conductive plates (FFPs) formed by being stacked in layer, the first conductive plate and the second conductive plate include linear regions elongated to face each other along a longitudinal direction in which a length with which source region and drain region elongated in parallel face each other is longest, and are elongated in a short-side direction orthogonal to the longitudinal direction. Here, high voltage wiring of either one of source wiring and drain wiring is elongated in the short-side direction to intersect the linear regions of the first conductive plate and the second conductive plate, and low voltage wiring of the other one of source wiring and drain wiring is elongated in the short-side direction to intersect at least one linear region of the first conductive plate or the second conductive plate.

Semiconductor device

A semiconductor device having a silicon-on-insulator (SOI) structure in which a source region and a drain region extend along a longitudinal direction that is a direction along a longer side of sides facing each other, and are disposed side-by-side in a lateral direction that is a direction perpendicular to the longitudinal direction. In a plan view, a body region extends along the longitudinal direction and is surrounded by a drift region and an insulating region. A space between the insulating region and the body region in the lateral direction becomes narrower from the center to the end of the body region in the longitudinal direction. This achieves high breakdown voltage in the semiconductor device.

A semiconductor device has on a semiconductor layer: a gate insulating film formed, extending from a second emitter region toward a buffer region beyond a first body region, and covering part of a drift region; and a gate electrode. The second emitter region contacts a first emitter region, and extends laterally to a portion under the gate electrode so as to be longer than a diffusion depth of the second emitter region and not beyond a lateral length of the first body region under the gate electrode, in an area from an end portion of the first emitter region closer to the gate electrode to a region under the gate electrode.

The present invention mainly provides an ESD protective element which can be built in high voltage semiconductor integrated circuit devices without increasing the chip area. An ESD protective element according to one embodiment has a construction comprising a semiconductor layer, a first region of a first conduction type formed in the semiconductor layer, a first region of a second conduction type formed in the semiconductor layer away from the first region of the first conduction type, a second region of the second conduction type formed in the first region of the second conduction type and has a higher impurity concentration than it, and a second region of the first conduction type formed in the second region of the second conduction type and has a high impurity concentration. The first and second regions of the second conduction type are in an electrically floating state.

ESD protective element and plasma display including the ESD protective element

In a semiconductor device of the present invention, a first base regionis extended to a part under a gate electrodewhile having a vertical concentration profile of an impurity that increases from the surface of a semiconductor layerand becomes maximum under an emitter region, and the length in the lateral direction from a point where the impurity concentration becomes maximum located under an end of the gate electrodeto the boundary with a second base regionis not smaller than the length in the vertical direction from the point where the impurity concentration becomes maximum to the boundary with the second base region

Lateral insulated gate bipolar transistor having a retrograde doping profile in base region and method of manufacture thereof

A high breakdown voltage semiconductor device is formed using an SOI substrate comprising a support substrate, an insulating film, and an active layer. The high breakdown voltage semiconductor device comprises an N-type well region and a P-type drain offset region formed on the active layer, a P-type source region formed on the well region, a P-type drain region formed on the drain offset region, a gate insulating film formed in at least a region interposed between the source region and the drain offset region of the active layer, and a gate electrode formed on the gate insulating film. The device further comprises an N-type deep well region formed under the drain offset region. A concentration peak of N-type impurity for formation of the deep well region is located deeper than a concentration peak of P-type impurity for formation of the drain offset region.

High breakdown voltage semiconductor device and fabrication method of the same

In a semiconductor device of the present invention, a first base regionis extended to a part under a gate electrodewhile having a vertical concentration profile of an impurity that increases from the surface of a semiconductor layerand becomes maximum under an emitter regionand the length in the lateral direction from a point where the impurity concentration becomes maximum located under an end of the gate electrodeto the boundary with a second base regionis not smaller than the length in the vertical direction from the point where the impurity concentration becomes maximum to the boundary with the second base region

Provided is a semiconductor device which includes a conductive bonding pad formed on a semiconductor substrate of the first conduction type via an insulating film and a diffusion layer of the second conduction type formed on a surface of the semiconductor substrate under the bonding pad. Characteristics do not deteriorate even when a breakdown occurs during wire bonding.

An object of the present invention is to provide a semiconductor device that is able to realize a low on-resistance maintaining a high drain-to-source breakdown voltage, and a method for manufacturing thereof, the present invention including: a supporting substrate; a semiconductor layer having a Ptype active region that is formed on the supporting substrate, interposing a buried oxide film between the semiconductor layer and the supporting substrate; and a gate electrode that is formed on the semiconductor layer, interposing a gate oxide film and a part of a LOCOS film between the gate electrode and the semiconductor layer, wherein the Ptype active region has: an Ntype source region; a P type body region; a Ptype back gate contact region; an N type drain offset region; an Ntype drain contact region; and an N type drain buffer region that is formed in a limited region between the N type drain offset region and the P type body region, and the N type drain buffer region is in contact with a source side end of the LOCOS film and is shallower than the N type drain offset region.

Semiconductor device and method for manufacturing the same

An object of the present invention is to provide a semiconductor device which enables to reduce the device area, while securing the breakdown voltage between the drain and the source of each MOS transistor for the semiconductor device including plural MOS transistors, which are arrayed adjacently each other, with different types of channel conductivity. The semiconductor device includes a semiconductor substrate, a buried oxide film and a semiconductor layer, and furthermore the semiconductor layer has an island-like semiconductor layer, in which a MOS transistor is formed, the MOS transistor has a source region, and a drain region that is positioned in the periphery of the source region, an island-like semiconductor layer, in which a MOS transistor is formed, the MOS transistor has a drain region, and a source region that is positioned in the periphery of the drain region, an isolation trench which isolates the former island-like semiconductor layer from other portions of the semiconductor layer, an isolation trench which isolates the latter island-like semiconductor layer from other portions of the semiconductor layer, and a buffer region, in which the electric potential is fixed to the lowest electric potential in a circuit, which prevents an electrical interference occurred between transistors.

In a high voltage P-channel MOS transistor formed on a silicon-on-insulator (SOI) substrate, a P-type source region (), an N-type body region () and an N-body contact diffusion region () are surrounded by a P-type drain region () and a P-type drift region (). A gate electrode () is formed to overlap the end portion of the N-type body region (). The end portion of the N-type body region () has a portion in which the gate electrode () and the P-type source region () are not adjacent to each other.

Lateral semiconductor device

A high withstand voltage lateral semiconductor device capable of improving its on-state breakdown voltage and safe operation area (SOA) without lowering its current capabilities, and structured so as to be easy to produce. The lateral semiconductor device comprises a second conductivity type second semiconductor region formed in a semiconductor layer so as to be adjacent to or away from a first semiconductor region, a second conductivity type source region, a second conductivity type drain region, and a gate electrode formed on a gate insulating film formed between an end of the source region on the surface of the semiconductor layer and an end of the second semiconductor region, wherein the first semiconductor region is extended from under the source region to partly under the gate electrode, the concentration distribution of a first conductivity type impurity increases in the region ranging from the surface of the semiconductor layer to the embedded insulating film and has a peak under the source region, and the impurity concentration in the semiconductor layer ranging from directly under the first semiconductor region to the embedded insulating film is lower than the surface concentration in the first semiconductor region.

Lateral semiconductor device and method for producing the same

A gate electrode has an end extended over a part of a LOCOS oxide film, and a source electrode has an end extended further than the end of the gate electrode over a part of the LOCOS oxide film. An insulating film covering the gate electrode and the LOCOS oxide film is formed such that the thickness of the insulating film at an end-portion region, which is on an end portion of the gate electrode provided to extend over a part of the LOCOS oxide film, as viewed from a main surface of a supporting substrate, is smaller than the thickness of the insulating film below an end portion of the source electrode above the drain region and smaller than the thickness of the insulating film on an end portion of the gate electrode above a body region.

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Nara, Japan

Teruhisa Ikuta