Oki Electric Industry Co., Ltd.

Oki Semiconductor Co., Ltd.

Lapis Semiconductor Co., Ltd.

Oki Electric Co., Ltd.

Teruhiro Harada

Shooji Kitazawa

Masayuki Otsuka

Satoru Namaki

Takashi Ono

Nobukazu Murata

Hiroyuki Tanikawa

Shuhei Kamano

Hiroshi Kuwabara

Keiichiro Takeda

Shoji Kitazawa

Keichiro Takeda

A nonvolatile semiconductor memory device of the charge trap type is initialized by reading the memory cells in the device to determine which charge traps hold less than a predetermined minimum charge and injecting charge into these charge traps until all of the charge traps in the device hold at least the predetermined minimum charge. The charge traps are then programmed selectively with data. The initialization procedure shortens the programming procedure by narrowing the initial distribution of charge in the charge traps, and leads to more reliable reading of the programmed data.

Nonvolatile semiconductor memory device and programming method

In a semiconductor nonvolatile memory, plural first nonvolatile memory cells are arranged in the memory array. Plural memory areas are arranged in the memory array and have plural second nonvolatile memory cells which store the same predetermined information. A sequence circuit generates a memory address, a latch selection signal, and a control signal at predetermined timings when a power is turned on. A write-read unit writes and reads information to and from the memory array and the memory areas based on the memory address and the control signal. A latch circuit latches the predetermined information, read by the write-read unit, based on the latch selection signal. A selection-drive unit selects the first or second nonvolatile memory cells based on the memory address and the predetermined information latched by the latch circuit, and applies a predetermined voltage to drive the selected first or second nonvolatile memory cells.

Semiconductor nonvolatile memory trimming technique for output characteristic control and redundancy repair

An internal step-down power supply circuit has an internal step-down power-supply output node, a driver, a divider circuit and a current mirror circuit. The internal node provides an internal step-down power supply potential. The driver adjusts an external power-supply potential and provides an adjusted external power-supply potential to the internal node. The divider circuit divides a voltage that appears on the internal node and provides a divided voltage. The current mirror circuit is connected to the divider circuit. The current mirror circuit compares the voltage provided by the divider circuit and a reference voltage. The current mirror circuit sets the conductance of a first transistor feeding a current in response to the reference voltage to n times of the conductance of a second transistor feeding a current in response to the voltage provided from the divider circuit, wherein n is greater than 1.

Internal step-down power supply circuit

A nonvolatile semiconductor memory device includes a plurality of memory cells. A couple of bits of data can be stored in the memory cell, the stored data being controlled according to resistance values of first and second variable resistance regions. One of the plurality of memory cells shares its first diffusion layer with an adjacent memory cell and shares its second diffusion layer with another adjacent memory cell. The first diffusion layers of the plurality of memory cells are coupled to each other with a first conductive line extending in a first direction. The second diffusion layers of the plurality of memory cells are coupled to each other with a second conductive line extending in the first direction. The gate electrodes of the plurality of memory cells are coupled to each other with a third conductive line extending in a second direction, which is orthogonal to the first direction.

Nonvolatile semiconductor memory device

The voltage translator uses a PMOS transistor connected to a positive voltage source and a wordline, an NMOS transistor connected to a voltage source lower than the earth potential and a wordline as output stages, and has a PMOS transistor having a feedback function which is connected to the positive voltage source and an NMOS transistor having a feedback function which is connected to a voltage source lower than the earth potential. In the voltage translator, not only the positive voltage but a voltage lower than the earth potential as well is supplied to a selected wordline.

Voltage translator

An internal step-down power supply circuit improves response performance (transition from a standby state to an active state in particular) of a system, without increasing current consumption. The internal step-down power supply circuit includes an output node for outputting an internal step-down power-supply potential; a driver for adjusting an external power-supply potential VDD and supplying it to the output node; a divider circuit for dividing a voltage developed at the output node and outputting the divided voltage; and a differential amplifier for comparing the divided voltage and a reference voltage. The differential amplifier outputs a voltage equivalent to twice a predetermined gain. The operational amplifier sets the conductance of first transistors for feeding a current responsive to the reference voltage to twice or more the conductance of second transistors for feeding a current responsive to the divided voltage.

A nonvolatile semiconductor memory comprises a cell bias circuit supplying a first voltage, a memory cell array having memory cell transistors, word lines, drain lines disposed perpendicular to the word lines and source lines disposed perpendicular to the word lines. the nonvolatile semiconductor memory further comprises source line equalizing transistors connected between the cell bias circuit and the source lines, respectively, the source line equalizing transistors turning on during a stand by mode, drain line equalizing transistors connected between the cell bias circuit and the drain lines, respectively, the drain line equalizing transistors turning on during the stand by mode, bit lines, main source lines, source line selecting transistors connected between the main source lines and the source lines, respectively, the source line selecting transistors turning off during the stand by mode, drain line selecting transistors connected between the bit lines and the drain lines, respectively, the drain line selecting transistors turning off during the stand by mode and a detecting circuit connected to said bit lines for supplying the first voltage to the bit lines for detecting data stored in the memory cells.

Nonvolatile semiconductor memory circuit capable of high-speed data reading

A semiconductor memory circuit of the present invention comprises a word line, a bit line, a memory cell transistor having a first terminal applied to a first electrical potential, a second terminal connected to said bit line and a gate connected to the word line, a reference bit line, a reference cell transistor having a first terminal applied to the first electrical potential, a second terminal connected to the reference bit line and a gate connected to the word line, a sense node electrically connected to the bit line, a reference node electrically connected to the reference bit line, a differential amplifier having a first input connected to the sense node, a second input connected to the reference node and an output, a first load circuit connected between the sense node and a second potential source, a second load circuit connected between the reference node and the second potential source and a test circuit receiving a test signal. The first load circuit has a first resistance value. The second load circuit having a second resistance value that is lower than the first resistance value. The test circuit changes the first and second resistance values in response to the test signal.

Nonvolatile semiconductor memory with testing circuit

In a method of reading data comprising the steps of selecting a given column line and a bit line adjoining to the column line among a plurality of column lines (102-1.about.102-3) and bit lines (101-1, 101-2)based on column selection signals (Y.sub.1 .about.Y.sub.3), selecting a given row line among a plurality of row lines (103-1.about.103-n) based on row selection signals (X.sub.0 .about.X.sub.n) and reading out data which is stored in memory cells (104-01.about.104-n4) each of which is coupled to the given column line and the row line to the selected bit line, the given column line is set at a first potential level (a potential level supplied by a voltage regulator circuit 160) and almost at the same time the selected bit line is set at a second potential level (a potential level supplied by a sense amplifier circuit 150) which is lower than the first potential level and unselected column lines are set at a third potential level (ground potential level or a potential level supplied by the potential supply circuit 190) which is lower than the second potential level to read out data. As a result, it is possible to perform a high-speed data reading. Moreover, it is possible to realize low power consumption since there flows no useless current at a standby state.

Method of reading data and read-only memory circuit

A semiconductor integrated circuit device chip mounts a group of voltage amplifier circuits and a group of output transistors on the surface thereof. The group of voltage amplifier circuits are arranged at an area remote from the group of output transistors on the chip to prevent the voltage amplifiers from operating erroneously due to a potential variation caused by a switching operation of the output transistors.

Semiconductor memory device with noise immunity

The semiconductor memory device receives a first and a second pairs of input signals. Each of the pairs has a first and a second address signals which are complementary and substantially in phase. The semiconductor memory device comprises a pre-decoder for receiving the first and second pairs of input signals and outputting a first and second pre-decode signals. The first and second pre-decode signals are complementary signals and are substantially in phase with each other. The pre-decoder comprises a NAND gate for receiving the first input signals of the first and second pairs and outputting the first pre-decode signal and a NOR gate for receiving the second input signals of the first and second pairs and outputting the second pre-decode signal. The NOR gate and the NAND gate are electrically isolated from each other. The semiconductor memory device further comprises a row decoder coupled to the pre-decoder and word lines for selecting one of the word lines in response to the pre-decode signals and a memory array coupled to the row decoder through the word lines.

Semiconductor memory device having a CMOS decoding circuit

A read-only semiconductor memory device including memory elements arranged in a principal surface of the semiconductor substrate in a matrix to form MOS transistors. Each of the memory elements has first and second electrode regions formed in the principal surface so as to respectively constitute the first and second electrodes, insulative layers formed on the principal surface, and a control electrode layer formed via the insulative layers on the principal surface to constitute the control electrode. The control electrode layer is commonly connected to memory elements in the lateral direction of the matrix. The first and second electrode regions are respectively arranged such that any adjacent two in the vertical direction of the memory elements electrically share the first and second electrodes, respectively. Each of the first electrode regions is interconnected to the first electrode region of one of the elements adjacent thereto in the lateral direction. The second electrode regions are also interconnected similarly. The device further includes first and second conductor members each formed on the insulative layers so as to electrically interconnect the first and second electrode regions, respectively, of the elements in the vertical direction. The boundaries between the control electrode layer and the first and second electrodes are defined in the lateral direction substantantially in parallel thereto.

Nonvolatile semiconductor memory device of shared contact scheme not

In a non-volatile memory device comprising a memory matrix having semiconductor memory cells arranged in rows and columns, a plurality of word lines are connected to the control gates of the semiconductor memory cells arranged in the rows and selected by a row decoder, a plurality of bit lines are connected to the sources of the semiconductor memory cells arranged in the columns and selected by a column decoder. Data lines are connected to the drains of a plurality of the semiconductor memory cells. A constant voltage application/current detect circuit applies a constant voltage to the drains of the semiconductor memory cells through the data line, and etects the current required to maintain the data line at the constant voltage.

Non-volatile semiconductor memory device

In a memory MOS semiconductor memory device comprising a memory matrix having semiconductor memory elements arranged in rows and columns, the memory elements in the same rows being connected to the respective word lines, and the memory elements in the same columns being connected to the respective source lines and data lines. A row decoder outputs a row selection signal to one of the rows of the memory elements through the word lines, while a column decoder outputs a column selection signal to one of the columns through the source lines. A common data line is electrically coupled to a plurality of the data lines, a constant voltage is applied from a common circuit to the data lines through the common data line, and the current required for maintaining the common data line at a constant voltage is detected by a detecting circuit.

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Kanagawa, Japan

Teruhiro Harada