Fujitsu Corporation

Teruhiko Kamigata

Hideo Miyake

Atsuhiro Suga

Hiroshi Okano

Yoshimasa Takebe

Hitoshi Yoda

Shigeru Kimura

Shinichiro Tago

Atsushi Ike

Yoshio Hirose

Taizo Sato

Yasuki Nakamura

Yasuhiro Yamazaki

Shin-ichiro Tago

Akiko Azegami

To provide a program performance analysis apparatus that can present to a user whether tuning made to a program operating on a predetermined hardware is either good or bad, a performance information acquisition unit for obtaining the performance information of a program, a difference information generation unit for generating difference information by making a comparison between the performance information of a first program and that of a second program obtained by making a change to the first program, and a change evaluation unit for evaluating whether the change is either good or bad are comprised.

Program performance analysis apparatus

A multiprocessing system includes a storage part that stores to a memory, a first operating system (OS) task set that is constituted by a combination of a first task and a first OS corresponding to the first task, the first task being designated by an execution instruction; and a task executing part that refers to the first OS task set stored to the memory, loads the OS constituting the first OS task set, and executes the first task designated by the execution instruction.

Multiprocessing system

An instruction processing method for checking an arrangement of basic instructions in a very long instruction word (VLIW) instruction, suitable for language processing systems, an assembler and a compiler, used for processors which execute variable length VLIW instructions designed based on variable length VLIW architecture.

Instruction processing method for verifying basic instruction arrangement in VLIW instruction for variable length VLIW processor

A multiprocessor system includes a plurality of processors, a shared bus coupled to the plurality of processors, a resource coupled to the shared bus and shared by the plurality of processors, and an exclusive control unit coupled to the plurality of processors and configured to include a lock flag indicative of a locked/unlocked state regarding exclusive use of the resource, wherein the processors include a special purpose register interface coupled to the exclusive control unit, and are configured to access the lock flag by special purpose register access through the special purpose register interface.

Multiprocessor system with high-speed exclusive control

An information processing device reads, buffers, decodes and executes instructions from an instruction store portion by pipeline processing includes: an instruction reading request portion which assigns a read address to the instruction store portion, an instruction buffering portion which includes a plurality of instruction buffers which buffer an instruction sequence read from the instruction store portion; an instruction execution unit which decodes and executes instructions buffered by the instruction buffering portion. A branching instruction detection portion detects a branching instruction in the instruction sequence read from the instruction store portion. A branch target address information buffering portion includes a plurality of branch target address information buffers which, when the branching instruction detection portion has detected a branching instruction, buffer the branch target address information for generating the branch target address of the branching instruction.

Processing device for buffering sequential and target sequences and target address information for multiple branch instructions

Data shared by plural processes of a program are identified and identification information is affixed to the shared data. When the program is linked by a linker, only the shared data to which identification information is affixed are extracted and a shared data area is created for the shared data. During program execution, this shared data area is prevented from being and the main memory is referred to or updated or the cache is invalidated prior to access of the shared data area by the linker. An address of data in a processor is computed from an address of the data in another processor based on a specific expression.

Method and apparatus for creating a load module and a computer product thereof

In a cache memory control method and computer of the present invention, a cache memory is connected to a main memory and divided into a plurality of cache blocks, and a lock/unlock signal is supplied to the cache memory to either set a replace-inhibition state of at least one of the cache blocks in which replacing at least one of the cache blocks to the main memory is inhibited, or reset the replace-inhibition state of at least one of the cache clocks such that replacing at least one of the cache block to the main memory is allowed. Either reading or writing of the main memory is performed by using the remaining cache blocks of the cache memory, other than the at least one of the cache blocks, such that, when the replace-inhibition state is set by the lock/unlock signal, replacing the at least one of the cache blocks to the main memory is inhibited during the reading or writing of the main memory.

Growing community of inventors

Kawasaki, Japan

Teruhiko Kamigata