Mitsubishi Denki Kabushiki Kaisha

Renesas Electronics Corporation

Renesas Technology Corp.

Teruhiko Amano

Fukashi Morishita

Kazutami Arimoto

Takahiro Tsuruda

Takeshi Fujino

Mitsuya Kinoshita

Tetsushi Tanizaki

Mako Kobayashi

Katsumi Dosaka

Naoya Watanabe

Mihoko Akiyama

Isamu Hayashi

Kenji Yoshinaga

Shinya Miyazaki

Masakazu Ishibashi

Masaki Tsukude

Kenji Yano

An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.

Content addressable memory with reduced power consumption and increased search operation speed

Content addressable memory

In a dummy word line region, a second metal interconnection line is arranged, and a connection between a low-resistive metal interconnection line constituting a word line arranged in a normal word line region and a lower gate electrode line is shifted. In a bit line twisting region, a memory cell gate electrode line is arranged to interconnect the gates of access transistors of memory cells, and a twisted bit line structure is implemented utilizing an upper metal interconnection line. A memory cell array region can more efficiently be used.

Semiconductor memory device with efficiently laid-out internal interconnection lines

In the configuration of a charge confinement type sense amplifier, activation/inactivation of a charge containing gate and activation/inactivation of a sense amplifier circuit are controlled by different control signals. Thus, a layout area of the sense amplifier for reading of internal data is reduced.

Semiconductor memory device having internal data read circuit excellent in noise immunity

A row including a defective memory cell is replaced by a row of redundant memory cell, independently in each of a pair of memory blocks on opposing sides of a pair of row decoders . A redundancy determining circuit for performing the replacement is provided for each memory block, and in the redundancy determining circuit , a plurality of fuse boxes are arranged. Accordingly, as the fuses are laid-out in efficient manner, a semiconductor memory device is provided in which the circuits can be effectively arranged on the chip.

Semiconductor memory device with improved layout and redundancy determining circuits

A power supply circuit and an oscillation circuit or the like of noise generation sources are concentrated, and the periphery thereof is surrounded by a guard ring. Guard ring is provided to have bonding pads at least partially thereon. Guard ring is effectively provided utilizing the region below bonding pads, so that effective noise reduction is achieved while preventing increase in chip area.

Semiconductor memory device capable of performing stable operation for noise while preventing increase in chip area

A control circuit portion which controls the operations of memory cells is concentrated in a central portion and heat radiation plates are placed thereon via adhesive. A semiconductor integrated circuit having a function of the MPU or the like is placed above the control circuit portion via a bump electrode. The control circuit portion and a memory block are formed on separate chips respectively.

Semiconductor memory device

A master control circuit provides access to a corresponding memory block via four local control circuits. The memory blocks are arranged so as to surround the master control circuit and the local control circuits. The amount of delay of a control signal to each memory block is set substantially equal to suppress skew in the control signal. A DRAM of high speed can be realized.

High speed operable semiconductor memory device with memory blocks arranged about the center

A semiconductor circuit device having a triple-well structure wherein a predetermined potential level is supplied to a top well without a contact region formed in the top well is disclosed. In an N-type ion implantation step for forming an N-type well region (,) in a P-type semiconductor substrate (,), a mask of a predetermined configuration is used so that ions are not implanted into a region of a portion which is to serve as a bottom portion (,B) of the well region (,). Then, the N-type well region (,) is formed which is shaped such that a portion (,) having P-type properties remains partially in the bottom portion (,B). The P-type portion (,) establishes electrical connection between a P-type well region (,) and the semiconductor substrate (,) to permit the potential applied to a contact region (,) to be supplied to the well region (,) therethrough. The portion (,) may include a plurality of portions (,) which allow uniform potential supply. This structure may be applied to basic cells of a memory cell array block.

Semiconductor circuit device having triple-well structure in semiconductor substrate, method of fabricating the same, and mask device for fabrication of the same

High speed operable semiconductor memory device with memory blocks

A rectangular semiconductor substrate region is divided into regions arranged in a plurality of rows and columns, and memory array blocks are provided to surround a central region. The plurality of memory array blocks are divided into a plurality of banks. Peripheral regions on both sides of the rectangular semiconductor substrate region are used as regions for providing sense amplifier power supply circuits, and circuits for generating a voltage to be transmitted onto word lines are provided at the four corner regions of the central region. Thus, a large storage capacity semiconductor memory device operating stably at a high speed and with reduced power consumption can be implemented.

Multi-bank clock synchronous type semiconductor memory device having

Regular memory cell arrays are arranged in divided regions in three rows and three columns except for the region located at the second row and the second column. The region located at the intersection of the second row and the second column is provided with a redundant memory cell array. The replacement operation of the regular memory cell arrays with the redundant memory cell array is provided for each memory cell block.

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Tokyo, Japan

Teruhiko Amano