The Boeing Company

Terry R Vogler

Young Kyu Song

Kyu-Pyung Hwang

Charles Muwonge

Benjamin A Westin

Thomas D Mitchum, Jr

An apparatus for designing a structural product includes memory to store computer-readable program code for an integrated development environment to establish a digital thread in a lifecycle of the structural product, and processing circuitry to execute the computer-readable program code. The apparatus is thereby caused to generate a graphical user interface from which the integrated development environment is accessible to cause the apparatus to generate an electromagnetic effects (EME) model of the structural product from authoritative data including a solid model of the structural product, and parameterize the EME model with one or more electrical properties. The apparatus is caused to produce a computational electromagnetics (CEM) model of the structural product from the parameterized EME model, perform a CEM analysis from the CEM model to generate a corresponding solution is generated, and post-process the corresponding solution.

Integrated development environment to establish a digital thread in the lifecycle of a structural product

In one or more embodiments, a method of manufacturing a high impedance surface (HIS) apparatus comprises patterning a first conducting layer on a core to form a first set of conducting pads, and patterning a second conducting layer on the core to form a second set of conducting pads. The method further comprises applying solder paste to each of the conducting pads of the second set of conducting pads. Also, the method comprises placing chip capacitors on the solder paste on the second set of conducting pads. In addition, the method comprises applying underfill between the chip capacitors. Also, the method comprises applying solder paste to each of the conducting pads of the first set of conducting pads. In addition, the method comprises placing chip inductors on the solder paste on the first set of conducting pads. Further, the method comprises applying underfill between the chip inductors.

Methods of manufacturing a high impedance surface (HIS) enhanced by discrete passives

In one or more embodiments, a high impedance surface (HIS) apparatus comprises a core; a first set of conducting pads, where a first side of the first set of conducting pads is connected to a first side of the core; and a second set of conducting pads, where a first side of the second set of conducting pads is connected to a second side of the core. The apparatus further comprises a plurality of chip inductors, where at least a portion of the chip inductors are connected to a second side of the first set of conducting pads; and a plurality of chip capacitors, where at least a portion of the chip capacitors are connected to a second side of the second set of conducting pads.

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Charleston, SC, United States of America

Terry R Vogler