Micron Technology Incorporated

Round Rock Research, LLC

Other

Mircon Technology, Inc.

Advanced Memory International, Inc.

Terry R Lee

Joseph M Jeddeloh

Kevin J Ryan

Jerry Michael Brooks

David J Corisis

Walter L Moden

Warren M Farnworth

Larry Duane Kinsman

Brent Keeth

Roy Edgar Greeff

John Frederic Schreck

Rahul Advani

Troy A Manning

Mark E Tuttle

David K Ovard

Mark Hiatt

Mike Brooks

Scott E Schaefer

Victor Y Tsai

Roger D Norwood

Robert N Leibowitz

Terry R Walther

Bharath Nagabhushanam

Ernest J Russell

Peter B Gillingham

Brian L Johnson

David V James

George Edward Pax

Chris G Martin

Cormac Michael O'Connell

Mark R Thomann

Bruce Millar

Thomas W Voshell

Yoshikazu Morooka

Wallace E Fister

Kim M Pierce

Henry Stracovsky

Desi Rhoden

Donald N North

Mark J Hiatt

Paul M Fuller

Mark Rogers Tuttle

Hans A Wiggers

Mike Pearson

David B Gustavson

Ron Harrison

Jean Crepeau

Roy Greeff

Victor Tsai

Robert N Bowitz

David Ovard

Some embodiments include apparatus, systems, and methods having a base, a first die, a second arranged in a stacked with the first die and the base, and a structure located in the stack and outside at least one of the first and second dice and configured to transfer signals between the base and at least one of the first and second dice.

Signal delivery in stacked device

A telescopic pole mounting system is provided. The system comprises an adjustable spacer, a first end of the spacer coupled to a bracket and a clamp that partially encircles a vertical pole, ends of the clamp attached to the bracket. The system also comprises a cup attached to the spacer, movement of the cup causing one of expansion and contraction of the spacer. The system also comprises a telescopic pole that attaches to the cup, and raises and lowers the coupled clamp, spacer, and cup when the clamp is in loosened state. The telescopic pole also turns the cup in a first direction to expand the spacer and push the bracket away from the vertical pole, thus tightening the clamp about the vertical pole. The telescopic pole also turns the cup in a second direction to contract the spacer, thus loosening the clamp about the pole.

Telescopic pole mounting system

A layout for simultaneously sub-accessible memory modules is disclosed. In one embodiment, a memory module includes a printed circuit board having a plurality of sectors, each sector being electrically isolated from the other sectors and having a multi-layer structure. At least one memory device is attached to each sector, the memory devices being organized into a plurality of memory ranks. A driver is attached to the printed circuit board and is operatively coupled to the memory ranks. The driver is adapted to be coupled to a memory interface of the computer system. Because the sectors are electrically-isolated from adjacent sectors, the memory ranks are either individually or simultaneously, or both individually and simultaneously accessible by the driver so that one or more memory devices on a particular sector may be accessed at one time. In an alternate embodiment, the printed circuit board includes a driver sector electrically isolated from the other sectors and having a multi-layer structure, the driver being attached to the driver sector.

Apparatus and methods for a physical layout of simultaneously sub-accessible memory modules

A method that dynamically adjusts link control parameters of a communications network. The communications network includes a transmitter coupled through a first data link to a receiver. The transmitter and receiver each have at least one associated link control parameter that affects the operation of that component. According to one method, data signals are transmitted over the first data link and the transmitted data signals are captured. The values of the captured data signals are compared to expected values for those signals, and the values of the link control parameters are adjusted to successfully capture the transmitted digital signals.

Dynamic synchronization of data capture on an optical or other high speed communications link

A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided into a plurality of ranks. The memory hub is operable to configure the memory module to simultaneously address any number of ranks to operate in a high bandwidth mode, a high memory depth mode, or any combination of such modes.

Reconfigurable memory module and method

A semiconductor device includes a memory array that has dynamic memory cells. In a self refresh test mode, a self refresh test mode controller monitors and/or controls various blocks and internal signals in the semiconductor device. The self refresh test mode controller may communicate with a remote testing device through various conductors including one or more DQ lines and/or one or more address lines.

Semiconductor device with self refresh test mode

The signal integrity of a high speed heavily loaded multidrop memory bus is often degraded due the numerous impedance mismatches. The impedance mismatches causes the bus to exhibit a nonlinear frequency response, which diminishes signal integrity and limits the bandwidth of the bus. A compensating element, such as a capacitor which ties the bus to a reference plane (e.g., a ground potential), or an inductor wired in series with the bus, is located approximately midway between the memory controller and the memory slots. The use of the compensating element equalizes signal amplitudes and minimizes phase errors of signals in an interested frequency range and diminishes the amplitudes of high frequency signals which exhibit high degrees of phase error. The resulting bus structure has increased desirable harmonic content with low phase error, thereby permitting the bus to exhibit better rise time performance and permitting a higher data transfer rate.

Capacitive multidrop bus compensation

A memory module is coupled to a number of controllers. The memory module is configured to configure each of a number of data input/output ports thereof as at least one of an input and an output in response to a first command from a particular controller of the controllers. The memory module is configured to partition itself into memory partitions in response to a second command from the particular controller so that each memory partition corresponds to a respective one of the controllers. Each of a number of data input/output ports of the controllers is configurable as at least one of an input and an output to correspond to a respective one of the input/output ports of the memory module. The first and second commands may originate from the particular controller, or the controllers may be coupled in parallel to the memory module.

Memory module with configurable input/output ports

Optically-coupled memory systems are disclosed. In one embodiment, a system memory includes a carrier substrate, and a controller attached to the carrier substrate and operable to transmit and receive optical signals, and first and second memory modules. The module substrate of the first memory module has an aperture formed therein, the aperture being operable to provide an optical path for optical signals between the controller and an optical transmitter/receiver unit of the second memory module.

Apparatus and methods for optically-coupled memory systems

A computer system includes a memory hub controller coupled to a plurality of memory modules. The memory hub controller includes a memory request queue that couples memory requests and corresponding request identifier to the memory modules. Each of the memory modules accesses memory devices based on the memory requests and generates response status signals from the request identifier when the corresponding memory request is serviced. These response status signals are coupled from the memory modules to the memory hub controller along with or separate from any read data. The memory hub controller uses the response status signal to control the coupling of memory requests to the memory modules and thereby control the number of outstanding memory requests in each of the memory modules.

System for controlling memory accesses to memory modules having a memory hub architecture

Growing community of inventors

Boise, ID, United States of America

Terry R Lee